IEEE Solid-State Circuits Magazine - Spring 2016 - 49

not disturb the NVM resistance for
the cells close to the driver.
The sneak path problem is associated with the IR drop problem.
Take the V/2 scheme as an example. The half-selected cells along
the selected WL and BL form the
sneak paths during the write operation. The sneak paths contribute
additional current to the IR drop
and further degrade the write margin. Meanwhile, the sneak paths
increase the write current (thus
the write power) that is provided
by the driver transistors at the
edge of the cross-point array. Further discussions about the IR drop
problem and the sneak path problem of the cross-point array architecture can be found in [26]-[28].
The conclusions from these works
indicate that increasing the LRS
resistance (or equivalently reducing the write current) and increasing the I-V nonlinearity of the NVM
cell (with the help of the selector) are useful to minimize the IR
drop and sneak paths. Figure 3(d)
shows the SPICE simulation of the
write margin and write power as a
function of the cross-point array
size for different I-V nonlinearity
(N ). The nonlinearity is defined as
the current ratio between Vw and
Vw /2. The NVM cell resistance is
fixed at 40 kX , and the wire width

is fixed at 20 nm in this study. It
is seen that at least N >1, 000 is
needed for maintaining sufficient
write margin and minimizing write
power for a large array (e.g., a
1,024 × 1,024 array).

Selector Device for
Cross-Point Array
Next we will survey the two-terminal
selector devices reported in [29]. For
unipolar switching (e.g., PCRAM), a
p-n diode is the most common device
for the cell selector. Although a highperformance p-n diode is easily fabricated with epitaxial silicon technology
for the planar device structure, it is
not feasible to implement an epitaxial
silicon-based p-n diode at the BEOL for
3D integration because it is difficult
to grow epitaxial silicon on a metal
layer and a high processing temperature is required. On the other hand,
amorphous silicon allows for a BEOL
processing temperature (<400 oC).
But an amorphous silicon p-n diode
does not meet the requirement for
the current density for the NVM programming. For bipolar switching (e.g.,
RRAM), bidirectional nonlinearity is
required (note: a bidirectional selector
also works for unipolar PCRAM).
There are two types of bidirectional selectors: Type I: exponential I-V
and Type II: threshold I-V. Figure 4(a)
and (b) shows the representative I-V

Type I: Exponential I-V

Type II: Threshold I-V

Current (A)

1µ
VW /2

100 n

1µ
VW /2

100 n
10 n

10 n
1n

10 µ

10 µ
Current (A)

cells of the selected row see a read
voltage and all the other unselected
cells see zero voltage (in reality, due
to the IR drop along interconnect,
the voltage is not perfectly zero
though). The entire selected row can
be read-out in parallel if each column can have one S/A. However, the
pitch of S/As is typically larger than
the column pitch; thus, multiple
columns have to share one S/A. S/
As can be generally categorized into
two types [25]: voltage mode and
current mode. In practical designs,
the choice between voltage-mode
sensing and current-mode sensing
depends on the array size and the
NVM cell characteristics. The general conclusion is that for an array
with a long BL length or a higher
LRS resistance (smaller read-out
current), current sensing provides
faster access.
The cross-point array suffers
from two well-known design challenges: 1) the IR drop problem along
the interconnect wire and 2) the
sneak path problem through the
unselected cells. The IR drop problem becomes significant when the
WL and BL wire width scales to sub50-nm regime where the interconnect resistivity drastically increases
due to the increased electron surface scattering. For example, at
20-nm node, the copper interconnect resistance between two neighboring cells is ~2.93 Ω; thus, the IR
drop along the wire for a large array
(e.g., a 1,024 × 1,024 array) is no
longer negligible. The farthest cell
from the driver sees an interconnect
resistance +3 kX. If the NVM cell's
LRS resistance (typically a few kX
up to tens of kX) is comparable to
this interconnect resistance, a portion of the write voltage will drop on
the wire instead of the NVM cell. To
guarantee a successful write operation, the write voltage provided
from the driver has to be boosted
over the actual switching voltage of
the NVM cell to compensate for the
IR drop. However, the write voltage
cannot be boosted too much because
1/2 Vw (in the V/2 scheme) should

-3 -2 -1 0 1
Voltage (V)

-2

-1
0
1
Voltage (V)

(a)

(b)
Selector

RRAM

Selector+RRAM

Figure 4: representative i-v characteristics for a bipolar rram with (a) Type i selector
and a bipolar rram with (b) Type ii selector. sPice simulation is performed with the rram
compact model [38].

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016