IEEE Solid-State Circuits Magazine - Spring 2016 - 50

characteristics for a bipolar RRAM with
Type I selector and a bipolar RRAM
with Type II selector, respectively. The
metrics of selector performance are
1) the nonlinearity (N ) defined as the
current ratio between Vw and Vw /2,
which will determine how effective the
sneak current suppression is, and 2)
the drive current density (e.g., 10 MA/cm2
is required for 10-μA write current

high current drivability (>5 MA/cm2),
and the threshold voltage is claimed to
be adjustable from +0.3 V to +1.3 V
to match various RRAM characteristics.
Although substantial progress has
been made in the past few years, the
development of selector devices is
still a key challenge for implementing large-scale cross-point memory
architectures today. Most importantly,

Merging NVM technologies face challenges from
aspects of process compatibility, manufacturing
yield, performance variability, and reliability.
at the 10-nm node). Oxide/electrode
interface engineering or oxide/oxide
bandgap engineering with the tunneling current mechanism can be leveraged as Type I selector, e.g., Ni/TiO2/
Ni bidirectional selector [30]. In addition, Cu ion motion in the Cu-containing mixed-ionic-electronic-conduction
materials also show a good bidirectional exponential I-V for bipolar
switching RRAM, as demonstrated by
a series of works [31]-[33]. The aforementioned Type I selectors rely on an
exponential slope in the I-V curve to
turn on the selector, accompanied with
an increase of the current by several
orders of magnitude. Ideally, an abrupt
turn-on behavior with steep slope is
preferred, which is referred to as the
threshold switching (Type II). The
threshold selector typically exhibits a
hysteresis in I-V as it turns on above a
threshold voltage and turns off below
a hold voltage. Threshold switching
can be achieved in the metal-insulatortransition (MIT) Mott oxide materials such as NbO2 [34]. The drawback
of MIT-based threshold selectors is a
relatively small nonlinearity (typically
N <100 ). Besides Mott oxide materials,
an ovonic-threshold-switch based on
chalcogenide materials has been demonstrated to be an excellent threshold
selector [35]. Recently, a field-assistedsuperlinear-threshold selector has
been reported [36], which shows
outstanding nonlinearity (N >10 7 ),
steep turn-on slope (<5 mV/dec) and

S P R I N G 2 0 16

the selector device characteristics
must match the NVM device characteristics. Adding selector devices in
series with the NVM cell inevitably
increases the programming voltage
as part of the voltage is used to turn
on the selector device. For the bidirectional selector with exponential
I-V, the read sense margin generally degrades because the read-current for LRS is also suppressed. As
a result, it requires a much longer
time for sensing. As a reference, a
well-designed current-mode sense
amplifier can sense sub-100 nA readout current within 26 ns [37]. For the
threshold switching selector with
abrupt I-V, the read voltage has to be
boosted above the threshold voltage
of the selector; thus, it runs a risk
of disturbing the NVM resistance in
the read operation. Ultimately, it is
preferred that the NVM cell itself has
a built-in I-V nonlinearity thereby
eliminating the necessity of the
external selector device.

Recent Progress on
Prototype Chip Demonstration
There are two methods for integrating RRAM cells on top of the CMOS
circuits. The first approach is to fabricate the RRAM cells following the
front-end-of-line process (close to
the transistor fabrication at a lowerlevel interconnect). For example, the
RRAM cells can be deposited at the
contact via between the drain and

IEEE SOLID-STATE CIRCUITS MAGAZINE

metal 1, and this approach is typically employed in the 1T1R array
architecture. The second approach
is to fabricate the RRAM cells via
the BEOL process at the top-level
interconnect (decoupled from the
transistor fabrication). For example,
the RRAM cells can be deposited at
the contact via between metal 4 and
metal 5. One of the advantages of the
BEOL integration is that the peripheral circuits can be hidden underneath the cross-point array to save
the area as demonstrated in Panasonic's 8-Mb prototype chip [39].
Figure 5 summarizes the recent
prototype chip demonstrations of
various NVM technologies reported
in the major conferences. Figure 5(a)
shows the memory capacity versus year, and Figure 5(b) shows
the write/read bandwidth versus
year. PCRAM and RRAM have demonstrated >Gb-level capacity owing
to the smaller cell size (4 F2 using
cross-point array or 6 F2 using 1T1R
array with minimum sized transistor), while STT-MRAM's capacity
is only up to the 64-Mb level (cell
size is still >30 F2 owing to a larger
transistor used to deliver sufficient
write current in the 1T1R array and
a relaxed layout design rule). It is
noted that the bandwidth is related
to the input/output (I/O) interface.
NAND flash typically use page-program (e.g., 4 kb per page) to achieve
high bandwidth, although it has
slow write time per cell. Emerging
NVM macros typically do not use
wide-I/O (only 64- or 128-b interface)
but has fast write-time per cell. Despite
the narrow I/O, the emerging NVMs
remarkably improve the write/read
bandwidth over the NAND or NOR flash.
The data sheet of the prototype chip
parameters (e.g., capacity, performance,
etc.) can be accessed via the Arizona
State University Memory Trend [40].
Next we will present a few representative prototypes for each
emerging NVM.

STT-MRAM Prototypes
Toshiba reported a 64-Mb STT-MRAM
prototype chip using a 65-nm CMOS

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016