IEEE Solid-State Circuits Magazine - Spring 2016 - 51

process, featuring a 30-ns cycle time
[41]; more recently, Toshiba reported a
1-Mb STT-MRAM prototype chip using
a 65-nm CMOS process, improving the
write/read cycle to 3 ns [42]. TSMC
reported a 1-Mb STT-MRAM prototype
chip using a 40-nm CMOS process and
featuring a 10-ns read cycle time [43].
Qualcomm/TDK-Headway reported a
1-Mb STT-MRAM prototype chip using
a 40-nm CMOS process, featuring a
20-ns write/read cycle time [44].

PCRAM Prototypes

Different emerging NVM devices may have
different application spaces in the memory
hierarchy due to their unique characteristics.

Numonyx (now Micron) reported a
1-Gb 1T1R PCRAM prototype [45]. The
cell selection device is a bipolar junction transistor. The fabrication was
done in 45-nm process, and 9-MB/s
write bandwidth and 266-MB/s read
bandwidth were demonstrated. Samsung reported an 8-Gb cross-point
PCRAM prototype chip [46]. The cell
selection device is a silicon p-n diode.
The fabrication was done in a 20-nm
process. A 40-MB/s write bandwidth
has been demonstrated.

Replacing Existing Technologies
in Memory Hierarchy
Different emerging NVM devices
may have different application
spaces in the memory hierarchy due

106

128 Gb

Storage Capacity (Mb)

105

3D NAND

32 Gb
Flash

104

8 Gb
PCRAM

103

RRAM

102

64 Mb

STT-MRAM

101
100

RRAM Prototypes

2004

2006

2008

2010
Year
(a)

2012

2014

2016

1,000

RRAM
(ISSCC 2012)

Write Bandwidth (MB/s)

ITRI reported a 4-Mb 1T1R HfOx-based
RRAM prototype chip [47]. The fabrication was done in a 180-nm CMOS process. A single-level-cell operation with
7.2-ns read/write random access was
presented, and an MLC 2 b/cell operation with 160-ns write-verify scheme
was demonstrated. Panasonic reported
an 8-Mb cross-point TaOx-based RRAM
prototype chip [39]. The fabrication
was done in a 180-nm CMOS process. A
443-MB/s write throughput (64-b parallel write per 17.2-ns cycle) and a 25-ns
read access has been demonstrated. For
the embedded applications, National
Tsing-Hua University reported a 4-Mb
macro in 65-nm logic-compatible process [48] and a 1-Mb macro in a 28-nm
logic-compatible process [49]. For the
large-capacity standalone applications,
SanDisk/Toshiba reported a 32-Gb
cross-point OxRAM prototype chip with
a 24-nm cell half-pitch [50]. Both Panasonic and SanDisk/Toshiba's design
adopted a two-layer stacked cross-point
array architecture by sharing the BL to
increase the integration density (similar

Applications of Emerging NVM

to Intel/Micron's 3D X-point architecture
[51]). Recently, Micron/Sony reported a
16-Gb 1T1R CBRAM prototype chip [52].
The fabrication was done in a 27-nm
DRAM-like process. A 200-MB/s write
bandwidth and 1-GB/s read bandwidth have been demonstrated.

STT-MRAM
RRAM
(ASSCC 2007)
(ISSCC 2011)
STT-MRAM
(ASSCC 2006)
RRAM (ISSCC 2014)

100

NAND (ISSCC 2008)
Flash

10

NAND
(ISSCC 2010)

NAND
(ISSCC 2012)
NAND
(ISSCC 2011)
PCRAM
(ISSCC 2010)

Emerging
NVMs

PCRAM
(ISSCC 2011)

NOR
(ISSCC 2007)
1

100

1,000
Read Bandwidth (MB/s)
(b)

Figure 5: a summary of (a) memory capacity versus years and (b) write/read bandwidth
versus years. The data are collected from major conferences such as ieDm, isscc, and vlsi
from 2005 to 2015 [40].

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51
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
