IEEE Solid-State Circuits Magazine - Spring 2016 - 53

The second approach using vertical RRAM requires only one critical lithography step to define the
pillar electrodes after sequentially
depositing multilayer plane electrodes, making it a more promising
approach for reducing the fabrication cost. However, the cost per
bit analysis for these two 3D array
architectures is not sp intuitive.
Although the vertical RRAM saves
the fabrication cost, its minimal F
is not as small as that of the horizontal counterpart; thus, it has a
lower integration density because
the diameter of the pillar electrode
is limited by the following factors.
First, the aspect ratio of the pillar
electrode is limited by the etching
process capability of metal/dielectric multilayers. Second, the pillar
electrode resistance will drastically
increase at the nanoscale. As a rough
estimation, the vertical RRAM can
scale to F= 30 nm considering a pillar diameter (~20 nm) plus twice of
the RRAM oxide thickness (~5 nm).
If the horizontal RRAM can scale to
F= 10 nm with the help of the selector, then one layer of horizontal
RRAM has the same integration density as nine layers of vertical RRAM.
A further detailed analysis is
needed to assess the pros and cons of
these two 3D integration approaches.
The 3D horizontal cross-point array
still needs the help of the selectors to
address the sneak path problem as in
the case of 2D cross-point array discussed earlier. The 3D vertical crosspoint array prefers the built-in I-V
nonlinearity of the RRAM cell as it is

Two-Macro Scheme

Niche Market of Emerging NVMs
Emerging NVMs may find applications in a niche market. One example is as radiation-hard NVM for
aerospace electronics. Many experiments show that RRAM is robust
against the radiation effects such

Novel Applications
of Emerging NVMs
Beyond the conventional memory
applications, novel applications that
use emerging NVM are arising. For
instance, the use of emerging NVM as
the physical unclonable function as
hardware security primitive has been
proposed [66], [67], which leverages
the intrinsic variations in the emerging NVM's switching processes. The
use of RRAM as the reconfigurable
switch has also been proposed.

Beyond the conventional memory applications,
novel applications that use emerging NVM
are arising.
as total ionizing dose effect [62],
while the single-event-upset effect
observed in the RRAM 1T1R array
was attributed to the photocurrent
generated at the neighboring transistor's drain to body p-n junction
[63], which can be eliminated by
using silicon-on-insulator transistors. Besides the standalone NVM
applications, emerging NVMs are
also suitable for embedded applications. RRAM devices are especially attractive due to their good
compatibility with logic processes.
For instance, an embedded RRAM
solution has been introduced for a
28-nm technology node [64], [65].
Therefore, RRAM has great potential as MB-level embedded NVM for
micro-controller applications.

RRAM-based FPGA was designed [68]
and demonstrated [69]. The use of
RRAM as ternary content-addressable-memory for fast-searching big
data has been reported [70]. Adding
RRAM cells on top of the SRAM cell
enables the instant-on and instantoff power gating by storing data
from SRAM to RRAM locally before
going to standby mode, which saves
the latency and power to transfer
the data to off-chip or embedded
flash, as shown in Figure 7. Example of nonvolatile cache include
eight-transistor-two-resistor (8T2R)
nonvolatile SRAM [71] and the seventransistor-one-resistor (7T1R) nonvolatile SRAM [72]. The same principle
also applies to the nonvolatile register
and nonvolatile flip-flop design.

One-Macro Scheme

D
SRAM

difficult to add the external selector
on the sidewall. The problem is that
the middle electrode between the
selector and the RRAM cell will make
a short circuit of multiple layers.

nvSRAM
Macro

eFlash
(NVM)

Cell
(a)

Two 3D-Stacked RRAM Cells
6T SRAM
RL
RR

NVM Cell

2T RRAM
Switch: RSWL
SRAM Cell

BL/RRAM-CL
Sharing

RSWR

SWL
(b)

Figure 7: (a) Power-gating schemes: (a) two-macro with conventional embedded flash and one-macro with embedded nvm cells on top
sram cells. (b) eight-transistor-two-resistor (8T2r) nonvolatile sram. adapted from [71].

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016