IEEE Solid-State Circuits Magazine - Spring 2016 - 62

DAC

V1
G1

DAC

l1 = V1.G1

DAC

Word Line

Memristor Cell

DAC

Bit Line

l2 = V2.G2

Driver Circuits in Silicon Substrate
(a)

ADC

l = 11+ l2
V1.G1 + V2.G2

(b)

(c)

Figure 3: A memristive crossbar unit for analog dot product operations.

levels; but these buses (on multiple
DIMMs) are eventually multiplexed on
to a single shared DRAM channel that
carries data into the processor socket.
Thus, the high aggregate intra-DIMM
bandwidth isn't entirely available to a
conventional processor. Moving computational logic to the DIMM allows
the system to leverage the high intraDIMM bandwidth and linearly scale
available bandwidth as more DIMMs
are added to the system. In other
words, 3D-stacked TSVs are not the
only source of high bandwidth; onDIMM buses are a great (and cheaper)
alternative source. The NDC-module
design of Pugsley et al. [27] is optimized for high-bandwidth memory
access for a parallel workload, such
as in-memory MapReduce. It is not a
good fit for applications that cannot
be easily parallelized.
Computation can be placed near
DRAM memory [27], near NVM (PCM
and memristors [36]), or near flashbased solid-state drives [7]. Note
that the benefits of NDP are determined more by the ratio of intraand interpackage data bandwidths,
which can be high in most memory
technologies.

What Programming Models
Are Required?
This remains a key challenge in the
widespread adoption of NDP. Not only
does NDP require the programmer
to grapple with the usual challenges

S P R I N G 2 0 16

of parallel/distributed programming
(e.g., how is data partitioned across
the compute units, what are the
semantics/synchronization for dealing with shared data or serialized
critical sections), but the programmer
has to also identify the best location
(i.e., host processor or near-data processor or near-data accelerator) for
any computation. Consider the following example approaches to this
challenge. The NDC proposal of Pugsley et al. [28] does not introduce a
new programming model-it tries to
leverage an existing infrastructure
and developer base. That architecture
is targeted at a class of workloads
that can be handled by the intuitive
MapReduce programming model.
The PEI proposal of Ahn et al. [2]
requires the application developer
or compiler to identify individual
instructions that can be mapped
to functional units on the memory
device. The burden on the developer or compiler is low because the
PEI hardware automatically decides
where that instruction is best executed. The larger community realizes that we are moving in a direction
where specific computations will be
off-loaded to accelerators, whether
they are near memory or not. The evolution of these programming models
and standards will likely play out over
the next five years. NDP introduces a
significant wrinkle to this evolution
because of how caches/memory are

IEEE SOLID-STATE CIRCUITS MAGAZINE

asymmetrically exposed to the various processors.

In-Situ Computing
I will end this section with a discussion of a unique in-memory accelerator, a design that leverages emerging
memristive technology and a memory array organization that not only
stores data but also performs operations on that data.
Figure 3(a) shows a memristive
crossbar array, where cells are implemented as metal-oxide materials between overlapping word lines
and bit lines on different metal layers. The array has no access transistors, and it can be represented
logically as a grid of resistances, as
shown in Figure 3(b). Each cell can
be individually programmed by applying the appropriate combination
of voltage pulses at the word lines
and bit lines [45]. During a read operation, as depicted in Figure 3(c), a
set of voltages V1-VN are applied to
the N word lines. If the cell conductances of the first column are G1-
GN, the current emerging from the
first bit line can be represented as
V1 # G1 + V2 # G2 + ... + VN # GN,
based on Kirchoff's law. In other
words, the current in the first bit
line is the dot product of the vector
of input voltages and the vector of
cell conductances in the first column. In parallel, each of the bit lines
is now performing a dot product of

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016