IEEE Solid-State Circuits Magazine - Spring 2016 - 63

the same input voltage vector and
its vector of cell conductances. The
memristive crossbar array is therefore a powerful analog vector-matrix
multiplier that leverages Kirchoff's
law to perform a large number of
parallel multiply-accumulate operations. Digital-to-analog conversion is
required when providing input voltages, and similarly, analog-to-digital
conversion (ADC) is required before
the outputs can be buffered.
The previously given analog
dot-product unit can be very useful in accelerating applications that
involve dot products on large data
sets. Machine-learning applications
fit this bill. While noise and precision
are important concerns in analog
units, machine-learning applications
are known to be tolerant to noise.
An upcoming paper [36] shows how
a mixed analog-digital architecture,
ISAAC, can execute entire deep-learning algorithms at very high efficiency.
In-situ computing targets the biggest
bottlenecks in these algorithms-
storage, access, and compute for
many millions of parameters-with
a compact and parallel crossbar unit.
In spite of ADC overheads (which are
significant), ISAAC is able to achieve
efficiency gains of nearly 15× over a
state-of-the-art digital accelerator for
deep learning [6].
In general, any resistive-RAM cell
is a good candidate for use in such
an analog dot-product engine. HfOxbased memristors are an especially
good fit because of their high on/off
ratio. Since memristor cells exhibit
a nonlinear I-V curve, they can
also seamlessly apply sigmoid-like
activation functions to the dot-product operation, as is done in machine
learning algorithms. Another example of in-situ computing is the DRAMbased Automata Processor that can
accelerate algorithms that rely on
pattern-matching [42].

Auxiliary Features
The previous section discusses a variety of computational capabilities that
can be moved to the memory device;
these explicitly accelerate portions

of the application itself. We now turn
our attention to other useful functionalities that can be executed on
the memory device; such features
can improve overall system metrics
in an application-agnostic manner.
Many of the proposals in this section
target phenomena (such as endurance, iterative writes, and new error
types) that are more applicable to
emerging NVMs than to DRAM.

Compression
Memory compression was introduced in commercial products over a
decade ago, e.g., IBM MXT [41]. However,
that idea didn't catch on for a variety
of reasons.
■ The latency of compression and
decompression added a nontrivial
penalty to memory access times.
■ There is significant software/hardware complexity in managing compressed data: 1) it takes nontrivial
logic to estimate the location of a
compressed block, and 2) when a
block is modified and the new compressed version turns out to be larger, several other blocks may have
to be moved to make room for the
larger block.
■ Invasive changes are required to all
parts of the operating system (OS)
that deal with memory management.
The last few years have seen significant advancements that make
compressed memory a very attractive
choice today. First, new compression
algorithms, such as Base Delta Immediate (BDI) compression [25], are able
to achieve sufficiently large compression ratios for a sufficiently large set of
applications, while consuming fewer
than a handful of nanoseconds for
compression and decompression.
Second, new compression architectures [24] have been developed that,
in the common case, make it easier to
locate a compressed block, and avoid
shuffling data around when compressed blocks grow in size.
Third, recent papers [37], [32]
have made the argument that it is the
greed for higher memory capacity
that increases the OS complexity from
compression. Therefore, these papers

have made the case that compression
should be used for a variety of reasons
but not to tightly pack more blocks
into a limited space. So a 64-B storage area in memory is reserved for a
single 64-B data block, even though
the block may only consume a fraction of that storage after compression.
This leaves the OS page management
mechanisms unchanged. There are
many other benefits of reading/writing smaller blocks [37]: lower energy,
the ability to do more reads/writes in
parallel, higher endurance for NVMs,
the ability to add more metadata for
error correction, etc. Sathish et al.
[32] exploit some of these benefits
for a GPU and GDDR5 memory, while
Shafiee et al. [37] exploit them in the
context of CPUs and DDR3. Their approaches place only one burden on the
OS: managing compression metadata
in a separate region of memory. Even
this obstacle can be scaled; a recent
paper [22] shows how error correction
code (ECC) metadata can incorporate
compression metadata.
With these new technologies in place,
compression is a feature that no longer
needs heavy involvement from the processor or the OS. It could be a feature
that is entirely managed by logic on
memory devices, either in 3D-stacked
devices or on DIMMs, and completely
oblivious to the rest of the system.

Memory Timing
Just as the management of compression can be off-loaded to the memory devices, other low-level memory
management features can also be
off-loaded to memory. For example,
as DRAMs scale or as new NVMs
come to market, new problems might
emerge. Because of process variation, some regions of a die may be
faster than others, and some regions
may be more error prone than others. Similarly, operations that consume large amounts of current (e.g.,
writes in NVMs) will introduce static
or dynamic IR-drop and pose severe
worst-case constraints on DRAM timing parameters [38].
Rather than expose these so-called
"blemishes" or conservative worst-case

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016