IEEE Solid-State Circuits Magazine - Spring 2016 - 64

parameters to the system, memory
devices may choose to perform lowlevel timing management on their
own [23]. The processor issues read
or write commands to the memory
device, and the device figures out the
fastest sequence of commands that
can service that data. If the manufacturing process is highly problematic,
it leads to more complex management
circuits and higher performance than a
competitor that chooses to not provide
smart timing management.

Reliability
In many domains, error-correction
support within memory is a strong
requirement. Modern error-correction
solutions, especially those for chipkill
[8], incur significant overheads for
storage, energy, and in some cases
performance. As DRAM technologies
scale, errors may become more common. Instead of relying on the processor socket to implement a reliable
solution over an unreliable DRAM
platform, there is value in implementing a reliable DRAM platform in
the first place so that the processor
doesn't have to worry about error correction. The advantage in implementing an error correction solution in
DRAM (either in a 3D-stacked package
or on a logic chip on a DIMM or on the
DRAM die itself) is as follows: 1) the
processor need not be exposed to the
bandwidth overhead of fetching ECC
bits, 2) there is reduced data movement energy, and 3) error correction
solutions can be designed that are tailored to the specific vulnerabilities of
the vendor's manufacturing process.
Reliability will be an even bigger
concern in NVMs because of wearout,
drift, the iterative nature of writes,
and other interference effects [5].
With internal mechanisms to handle
these problems, memory vendors can
make trade-off choices that would
not otherwise have been palatable.
For example, one would not design a
weaker write process if it resulted in a
high raw bit-error rate being exposed
to the outside world. But with an inbuilt error correction process, a notso-perfect write mechanism may

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yield an overall lower power consumption, while also yielding a low
bit-error rate. Note that codes can
also be constructed to reduce data
transmission energy or reduce write
energy/wearout in NVMs, as is done
with data bus inversion in DDR4 or by
a few other recent papers [39], [19].

Security
It is clear that security is a metric that
will grow in prominence. A first step
in protecting sensitive information is
to encrypt data. There are good arguments for performing this encryption
(and corresponding decryption) on the
processor or on the memory. If one is
paranoid about an attacker having
physical access to the hardware and,
in particular, the memory bus, then
plain text information should never
emerge out of the processor socket,
and the encryption is best performed
on the processor. By giving the processor control over encryption, the
application can also lower overheads
by only encrypting the most sensitive
information. On the other hand, data
encryption on the memory device
makes sense if the threat model is that
someone may steal a DIMM. In such
cases, a more lazy encryption policy
can be implemented. One can also
implement an aggressive prefetchand-decrypt policy on the memory
device to reduce read latency; doing
this on the processor would incur a
heavy bandwidth penalty.
There exist other threat models that require more drastic security measures. If an attacker has
physical access to hardware (e.g., a
malicious cloud operator), we have
already seen that data encryption
is an important first step. Even with
data encryption, the attacker can
still engage in replay attacks [29]
(returning the old encrypted value
of data to disrupt the application)
or gather sensitive information [13],
[17] by snooping on the address trace
(note that addresses are still sent out
in plain text). To address these vulnerabilities, researchers have constructed solutions, Merkle trees [12]
and oblivious RAM [40], respectively,

IEEE SOLID-STATE CIRCUITS MAGAZINE

that organize memory blocks into
a logical tree structure and require
fetching all the blocks in a given
subtree. Both solutions incur a very
high penalty in terms of bandwidth.
Moving some of these solutions to
the memory device, as was done by
Gundu et al. [14], can lower the overheads by leveraging the high intrapackage or intra-DIMM bandwidth.

Closing Thoughts
In summary, this article has made
the argument that memory devices
can be much more than "dumb" units
that store rows of bits. They can be
augmented to perform parts of the
application or other auxiliary system-level features. This can directly
impact overall system performance
and energy. While this approach
will no doubt increase the cost per
bit for memory devices, it offers an
opportunity for value addition in an
era where customers will likely pay
more for specialized systems.

Acknowledgments
This work was supported in part by IBM
Research, Hewlett Packard Labs, and
by National Science Foundation grants
1302663 and 1423583. This article
draws heavily on the work of students
in the Utah Arch lab (Seth Pugsley, Ali
Shafiee, Akhila Gundu, Manjunath
Shevgoor, Anirban Nag, Niladrish Chatterjee, Meysam Taassori, and Arjun
Deb) and collaborators (Alper Buyuktosunoglu, Al Davis, Feifei Li, Naveen
Muralimanohar, Vivek Srikumar, and
Viji Srinivasan).

References

[1] J. Ahn, S. Hong, S. Yoo, O. Mutlu, and K.
Choi, "A scalable processing-in-memory
accelerator for parallel graph processing,"
in Proc. ACM/IEEE 42nd Annual Int. Symp.
ISCA, Portland, OR, 2015, pp. 105-117.
[2] J. Ahn, S. Yoo, O. Mutlu, and K. Choi, "PIMenabled instructions: A low-overhead,
locality-aware
processing-in-memory
architecture," in Proc. ACM/IEEE 42nd Annual Int. Symp. ISCA, Portland, OR, 2015,
pp. 336-348.
[3] B. Akin, F. Franchetti, and J. Hoe, "Data reorganization in memory using 3D-stacked
DRAM," in Proc. ACM/IEEE 42nd Annual
Int. Symp. ISCA, Portland, OR, 2015, pp.
131-143.
[4] R. Balasubramonian, J. Chang, T. Manning, J. Moreno, R. Murphy, R. Nair, and S.
Swanson, "Near-data processing: Insight

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