IEEE Solid-State Circuits Magazine - Spring 2016 - 67

DRAM Technology

feature sizes approach the quantum mechanical region.
To cope with those challenges, the
industry is developing new approaches
to scaling and architecture. For example, three-dimensional (3D) device
concepts are being introduced to flash
memory fabrication, and new types of
3D peripheral circuitry is being developed for DRAM.
This article will discuss the current state of the memory technology
landscape, beginning with a discussion of the background on the mainstream memories used today, the
technical challenges facing them,
and the technological advances
being used to overcome those challenges, as well as the landscape for
new and emerging applications.

Samsung Electronics' first semiconductor efforts weren't even
made until December 1974-27
years after William Shockley's
first transistors at Bell Labs and
late to an industry dominated
by American and Japanese
companies since Fairchild produced the first ICs. Samsung's
first semiconductor product, a 64-kb DRAM, wasn't
announced until 1983. Just
nine years later in 1992, Samsung was the first in the world
to produce a 64-Mb DRAM
chip and in 1993 became the
largest producer of DRAM,
a distinction the company
has held ever since.
Despite the quick scaling of the early days, modern DRAM shrink is facing
new technical limitations,
and the challenges are
likely to continue due to
the physical limitations
of photolithography
and patterning. Cuttingedge lithography techniques
such as extreme ultraviolet (EUV)
are promising for advanced scaling,
but the high cost and reduced wafer
throughput are limiting. Combining multiple patterning technologies
such as double patterning technology
(DPT) or quadruple patterning technology (QPT) with these photolithography technologies is
likely to be effective, but
increases to the process
complexity and cost burden are yet to be resolved.
Additionally, from a circuit
design point of view, characteristics of DRAM like variable-retention time may need
to be reconsidered as the
technology scales down [1].
While scaling DRAM to 18 nm
and below was once thought
to be impossible, Samsung
has managed the achievement

through extensive mask innovations and process modifications.
Samsung's new process technologies
ensure that DRAM scaling leadership
can continue into the future [2].
As bandwidth and power consumption are emerging as memory
system bottlenecks, smart design
of peripheral circuitry is another
essential component to the future of
DRAM technology. The latest DRAM
input-output (I/O) interfaces like
DDR4 (double-data rate) (see Figure 1) and LPDDR4 (low-power DDR)
were designed and standardized with
higher bandwidth and reduced supply voltage specifically to satisfy the
requirements of data-driven systems.
After the introduction of mobile
communication devices in the mid
1990s, the needs of low-power memory within the limited battery environment had been increased, and
LPDDR was introduced in the early
2000s, which has greatly reduced the
power consumption. In DDR DRAM,
2.5 V of power consumption was
reduced to 1.8 V, and standby power
was reduced as well with the support
of temperature compensated selfrefresh, partial array self-refresh,
and deep power down technologies.
The smartphone's appearance with
performance emphasized mobile
devices requested more bandwidth
of LPDDR, and 400 Mb/s bandwidth

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
