IEEE Solid-State Circuits Magazine - Spring 2016 - 68

Wire Bonding

TSV

Chip 4

Slave 3

Chip 3

Slave 2

Chip 2

Slave 1

Chip 1
PCB

Master
PCB

Memory Controller

FIGURE 1: The Samsung 20-nm-class DDR 4 using TSV techniques.

8 Gb 8 High
DRAM

1.8X

Buffer
Capacity

Power Efficiency
1.9X

8 Gb 4 High
DRAM

Bandwidth

Buffer
4 GB

8 GB
256 GB/s

*MPGA: Micro Pillar Grid Array

GDDR5

HBM

GDDR5

HBM

FIGURE 2: The Samsung 20-nm 4GB/8GB HBM has better performance and power efficiency when compared to GDDR5.

in LPDDR1 has increased to 1,066
Mb/s in LPDDR2, 1,866 Mb/s in
LPDDR3, and 4,266 Mb/s in LPDDR4.
Even with this performance increase,
energy efficiency has been improved
as well with 30~40% level among
each interface changes.
Additionally, novel 3D package
designs using through-silicon via
(TSV) and high-bandwidth memory
(HBM) are supporting future DRAM
demand. TSVs, where an electrical
connection passes through the silicon die vertically, are particularly
important to the realization of 3D
packages. Using a TSV system-inpackage for wide-IO memory and
application processors has reduced
memory interface power consumption by 10%, while increasing bandwidth [2]. TSVs could increase
memory area density by eight to 16
times, while providing a high-speed
interconnect, which makes the technology an ideal candidate for use in

S P R I N G 2 0 16

DDR3, DDR4, and next-generation
HBM modules (see Figure 2). Using
TSVs allows for up to four DDR3 or
DDR4 memory die to be stacked in
one package, reducing power consumption by 10% compared with
wire bonding, and achieving speeds
up to 3,200 Mb/s, the full bandwidth of DDR4 [2]-[3]. HBM, in particular, is an ideal use for TSVs. HBM
applications like high-end graphics, high-performance computing,
and high-end servers need more
than 1,000 I/O operations per second per pin and products exceeding
2.4 Gb/s are already being introduced to the market. Combined
with advanced packaging, reduced
power, and smaller form factors, the
advantages of TSV and stacked die
architectures are clear. With rapid
process maturity and a road to price
stability, we expect the technology
to be used throughout the memory industry. Eventually, emerging

IEEE SOLID-STATE CIRCUITS MAGAZINE

technologies like optical and wireless interconnects will complement
the wafer-stacking approaches of
today's silicon and keep pace with
the future data performance needs.
Of course, none of those advances
comes without some difficulty. For
mass production, HBM requires more
than 4,000 finely pitched vias and
bump interconnections per chip, and
the complexity increases with the manufacturing process. Research into batch
processes for TSVs on HBM such as
chip-on-wafer bonding and 2.5D interposers to connect processors directly
to memory blocks are under active
development [3]. TSV integration relies
on multitier interconnection, solutions for thin wafer handling, dissipation of the increased heat, reliable via
formation, and fine pitch (40 mm), all
of which must be implemented while
maintaining cost competitiveness.
In addition to process shrink
and packaging innovations, DRAM

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