IEEE Solid-State Circuits Magazine - Spring 2016 - 69

Flash Technology
Since its introduction in 1980s, flash
memory has been used in everything
from mobile phones to consumer
electronics, to enterprise storage.
Flash memory cells come in two
flavors: NOR type and NAND type,
both invented at Toshiba in the
1980s [4]. Early in the history of
flash, NOR flash memory made up
the vast majority of flash market
revenues, mostly as a code memory for mobile phones. As capacity
requirements for nonvolatile storage increased and process scaling
advanced, NOR gave way to NAND
as the most widely used technology.
NOR is still used in limited applications today, such as low-end phones
or other places where only a small
amount of storage is required.
Along with feature scaling, the
development of NAND with multiple
bits per cell has made a significant
contribution to cost reduction in
flash, cutting the cost per bit by
half and then two-thirds. However,
identifying tail bits from groups of
cells can sometimes be a challenge.
To overcome the limitations, flash
employs error checking and correction code to read tail bits and
manage errors from defects, data

retention failures, and program/
erase cycling stresses as well. The
use of error-correction code (ECC)

and even DPT and QPT are complicating process flows and reducing yields.
Second, interference coupling is be-

The history of semiconductors memory
is marked by continuous innovation
and advancement.
has enabled even further cost reductions by allowing for faster technology scaling, reduced development
times, and better yields.
Currently, advanced NAND production has reached midteen-nanometer node sizes where fabrication
and control of cell operations are
starting to get more difficult. The
productivity of EUV lithography is still
far behind industry requirements,

coming a significant barrier to flash
scaling. As the process scales down,
the space between adjacent cells is
getting smaller and creating capacitive coupling between cells. The coupling interferes with cell distribution
control, as shown in Figure 3(b), and
reduces the reliability of cell responses. Various techniques have been employed to deal with couplings, but as
the number of stored electrons falls

D/R
Over 30 nm

Over 30 nm

Cell

10 nm
e-

(a)
Probability Density Function (PDF)

is a key ingredient in enabling the
latest computer architecture innovations. With architectures requiring
a smaller gap between memory and
storage, the boundary between the
two is becoming increasingly fuzzy.
New types of memory have been
introduced to address these blurring
lines, but their lack of technical maturity and high price mean that it's too
soon for their widespread adoption.
Instead, to meet the needs of these
new architectures in the near term,
Samsung is developing new DRAM
technologies, including differentiated
features in bandwidth, latency, cost,
power, and reliability. These products
and others will be introduced to the
market soon, and their widespread
use in future computer architectures
will bring a new era for DRAM and the
memory industry.

0.07
0.06
0.05
P1 State

0.04

P2 State

P3 State

0.03
0.02
0.01
0
100

150

200
250
300 350 400
Normalized Threshold Voltage

450

500

No Progarm Interference
After Far-Neighbor (LSB) Interference
After Far-Neighbor (LSB + MSB) Interference
After Direct-Neighbor Interference
(b)
FIGURE 3: (a) Interference coupling and patterning difficulties [5] and (b) cell threshold voltage distribution reshaping due to interference coupling [6].

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016