IEEE Solid-State Circuits Magazine - Spring 2016 - 70

Almost since the introduction of NAND,
the market has been asking and searching
for alternative memory technologies to
complement DRAM and flash.
with scaling, the possible solutions
are limited.
The breakthrough to overcome
these issues was the introduction of
3D vertical NAND cell formation, first
driven by Samsung. (See Figure 4.) By

forming the cell vertically, the minimum feature size can be increased,
while maintaining cost-effectiveness, improving performance, and
reducing power consumption. This
increased feature size allows for bet-

Third-Generation V-NAND
First 3-b V-NAND Mass Production
V3

First V-NAND Mass Production
V2
V1

2011

2013

2014

2015

FIGURE 4: The evolution of 3D vertical NAND [7].

tPROG (a.u.)

X1/2

2D NAND
(16 nm)

3D NAND
(32 Tracks)

BER (a.u.)

(b)

(a)

2D NAND
3D NAND
X10

0 1 2 3 4 5 6 7 8 9 10
Cycle (K )
(c)

FIGURE 5: (a) A cross-sectional view of a 3D NAND and comparing (b) program speed
comparison and (c) endurance of 2D NAND and 3D V-NAND [2].

S P R I N G 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

ter controllability of cell operations
through higher coupling between the
control gate and storage node, while
the gate-all-around structure results
in significant improvements in
interference coupling by effectively
shielding each cell.
Performance improvement is another benefit of adopting 3D NAND
structures. In planar NAND, interference coupling from programing operations can disturb the values stored
in nearby cells. To alleviate these effects, the programming of multiple
bits per cell is divided across several
operations, slowing down the programming. With a 3D architecture, the
reduction in interference coupling
means that multiple bits per cell can
be programmed simultaneously. The
simplified program operation also
allows for a significant reduction in
power dissipation for programming
operations. Compared with planar
late 10-nm scale NAND, the program
time and power consumption of Samsung's third generation TLC V-NAND
is reduced by half. Another benefit
to 3D NAND is improved endurance.
(See Figure 5.) The result is a significant improvement in write endurance
over planar NAND.
Today, Samsung is shipping products based on a 48-layer cell V-NAND
technology and expects to continue
to increase the vertical height over
time. Additionally, the larger feature size allows for scaling to continue easily for several generations,
and efforts to extend it further are
underway. For example, by using
new materials, layers can be made
thinner, reducing the difficulty of
fabricating a high-aspect-ratio channel hole. V-NAND enables a long
future for flash memory economics
and performance.
Of course, flash memory does
have some natural limitations; it
inherently allows for only a limited
number of program and erase operations, as each operation requires the
physical movement of electrons
through holes in the dielectric layer.
Additionally, updating data in place
on flash is impossible because of the

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016