IEEE Solid-State Circuits Magazine - Spring 2016 - 71

mismatch in size between programs
and erase operations, resulting in
the complicated management flow
known as garbage collection [8]. Garbage collection has some data movement overhead, potentially taking
bandwidth away from drive operations, and may require two-to-five
times the program/erase cycles. This
acceleration in program and erase for
management is known as the write
amplification factor. To address these
issues, flash controllers implement
management software known as the
flash translation layer (FTL).
Initially, the FTL was run on the
host system, but managing flash
from the host led to several problems. First, the requirements for
FTL and error correction vary significantly between flash vendors
and technology generations, creating a very big job in implementing
and maintaining the software. Second, the NAND management system
consumes valuable host resources
and drains performance. Third, the
integration of NAND management
systems with host system software
required significant additional product development time, slowing the
time to market. As a result, managed
NAND was introduced to the market,
bringing the flash management software into a single device consisting
of NAND, controller, and software.
As the minimum feature size
moves below 20 nm, the burden
of error correction to control cell
distribution has reached a critical
mass. To maintain consistent operation at advanced nodes, new read
and program/erase algorithms need
to be devised. One example is read
retry, where the sensing level of a
cell is modified to find an optimal
spot for minimizing tail bits. Including read retry, there are various
algorithms implemented in FTL.
Flash memory technology will
continue to evolve over the coming
decades by combining cell structure changes, process technology
improvements, and supports from
both device's firmware and host software, and the solution-level integrity

that encompasses NAND, controller,
and software, including FTL, will be
increasingly important.

New Memory Technology
Almost since the introduction of
NAND, the market has been asking
and searching for alternative memory
technologies to complement DRAM
and flash. Device and process technology advancements have steadily
overcome scaling roadblocks, but it
is inevitable that new complications
will emerge as technology leaders

reliability mechanism are all still
precluding PRAM's widespread adoption. Nonetheless, PRAM still stands
out as the most advanced memory
device to ever achieve volume production.
SST-MRAM has been getting attention as a "complete" memory device
for some time now. Device speed is
expected to be comparable to DRAM,
the endurance is nearly unlimited,
and the latest STT concepts seem to
promise a secure path to easy scaling. Although there are on-going

Despite the quick scaling of the early
days, modern DRAM shrink is facing new
technical limitations.
pushes DRAM and NAND to higher
performance and smaller geometries.
The limitation of the inherent tradeoff between the speedy but volatile
DRAM and non-volatile but relatively
slow NAND has driven attention to the
search for new memory technology.
Samsung is no exception to this
pursuit. We continue to spend prodigiously on the R&D of relatively
well-known memory devices such as
phase change memory (PCM/PRAM),
spin-transfer torque magnetic memory (STT-MRAM) and resistive memory (RRAM), as well as other more
adventurous options such as memory based on carbon nanotubes.
Of these, the most practical and
best developed is PRAM. Samsung
was among the first volume producers of 1-Gb PCM back in 2006, supplying PRAM as a NOR replacement
for mobile devices. However, the
technology suffers from a significant
cost-efficiency deficit compared
with DRAM and NAND, particularly
as those devices have continued to
scale consistently (of which Samsung has high level of confidence
for at least the next five years).
Additionally, a significant asymmetry in read versus write latencies,
an unclear path to multilevel cell
(MLC) capability, and a complicated

challenges for volume production,
STT-MRAM seems to be an ideal candidate for mobile, Internet of Things
(IoT), and embedded solutions in
the near future. It will certainly be
interesting to observe how the small
density STT-MRAM market develops
over the next several years.
Resistive memory has a slightly
longer way to go. A few industry players have made a committed effort to
RRAM development, but progress to
date points to five or more additional
years of large-scale efforts.
Other alternative memories face
similar challenges. In terms of its
material properties, carbon nanotube
(CNT) memory is a strong candidate
for a new memory technology but
from an industry standpoint, CNTs
are too immature for serious consideration today. It remains to be
seen whether a mature, mass-production CNT memory is even technically and economically feasible.
Conservatively, we would expect the
viability of this more experimental
option to become clear over the next
three years.
Just as important to enabling a
new memory as the material properties of the media is its software and
system ecosystem. With our experience evangelizing for the adoption

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016