P-N Junction Diode V (n ) V (n ) V (n + 1) N+ V (n + 1) P+ N+ P-Well N-Well P-Substrate (b) (a) V (n ) V (n ) Schottky Barrier Diode PIN Diode V (n + 1) Metal P+ N+ N+ Equivalent Circuit of Ideal Charge Pump Intrinsic Poly Silicon V (n + 1) (d) (c) Saturation Mode Body Effect Reduction Triode Mode Booster Body Bias (e) (f) (g) FIGURE 1: A switching device structure. N-Well Capacitor (Standard CMOS Process) T2 Gate Capacitance MIM/PIP Capacitor (Mixed Signal LSI) T2 T1 Using Parasitic Cap Between Interconnection Layers T1 T2 Gate Poly Gate Poly N-Well T2 T1 (a) (b) (c) FIGURE 2: A capacitor structure. Capacitor An N-well capacitor can be fabricated without any additional process cost in a standard CMOS process [Figure 2(a)] [24]. The N-well terminal can be driven by a clock with a voltage range from 0 V to VIN. The gate oxide is usually thick enough to sustain a high voltage generated by a pump. There are some parasitic 84 S P R I N G 2 0 16 capacitance components associated with the pump capacitor, such as a junction capacitance between N-well and P-substrate, a fringe capacitance between the gate edge to the P-substrate, and wring capacitance to the gate and N-well. A nominal parasitic capacitance to the gate capacitance ratio is an order of 10%. When a charge pump is needed in a IEEE SOLID-STATE CIRCUITS MAGAZINE mixed signal large-scale integration (LSI), metal-insulator-metal or polysilicon-insulator-polysilicon capacitor may be available [Figure 2(b)]. But the capacitor is usually designed as a lowvoltage device. A nominal parasitic capacitance ratio can be on the order of 1%. When you have many interconnection layers in a certain technology node, parasitic capacitance between the layers can be used as a pump capacitor or a part of the pump capacitor [Figure 2(c)] [16]. In an ideal case where there is no parasitic capacitance and resistance and zero threshold voltage of switching device, the input current is given by (N + 1) times larger than the output current. We have N current paths through N-capacitors and one current path from the input terminal as shown in Figure 3(a). Using notation of the dc-dc voltage converter with a conversion ratio of (N + 1), the charge pump is expressed by an equivalent circuit shown in Figure 3(b). It is also matched with the fact that the maximum attainable voltage VMAX is given by (N + 1)VIN. As calculated in Part 1 [1], the output impedance RPMP is given by N/(fC) because there are N switched-capacitors between the input and output terminals and each switched capacitor has an effective resistance of 1/(fC). CPMP indicates an effective load capacitance associated with the internal pump capacitance to show dynamic behavior [17]. It is calculated to be about one-third of the total pump capacitors. As shown in Figure 3(b), power efficiency of the ideal charge pump is given by h = VOUT /VMAX . (3) Power Efficiency of Ideal Charge Pump We can focus on the conduction part shown in Figure 3(c) to understand how power efficiency is determined in steady state. It is identical to a linear