IEEE Solid-State Circuits Magazine - Spring 2016 - 85

regulator where the ideal power efficiency is given by the output voltage
over the input voltage as (3).
Let's look at the power efficiency
in a different view using Figure 3(d).
IOUT is the base, and voltage is the
height. As a result, the area describes
power. When VOUT is close to zero, POUT
is close to zero because most power
is loss. Therefore, power efficiency is
close to zero. When VOUT is close to
VMAX, the loss is close to zero. Therefore, power efficiency is close to one.
As a result, power efficiency increases
monotonically in ideal case, as shown
in Figure 3(e). Hence, the area ratio
(POUT/PIN) is equivalent to the height
ratio (VOUT/VMAX) because the base is
common no matter what IOUT is. Thus,
(3) holds. Figure 3(d) suggests POUT
has its maximal between VOUT = 0 V
and VOUT = VMAX.
Figure 4(a) identifies the optimum operating point where the output power is maximized [25]. The
upper graph shows the I OUT -VOUT
curve. The output power is a multiple of I OUT with VOUT, resulting in a
quadratic function as shown in the
lower graph. The maximum is given
at a half of VMAX because the X-inter-

It was concluded that Falke-Dickson [3], [4]
parallel voltage multiplier or charge pump was
best for integrated circuits where capacitors
and switching devices had significant
parasitic capacitance [5].
ceptions occur at zero and VMAX. The
maximum power is then given by

the following relation between RPMP
and VMAX is met

POUT- MAX = VMAX2 /4R PMP .

R PMP = VMAX / (2I L) .

On the other hand, h is 50% at most
when VOUT = VMAX/2 as given by (3).
One may have different load conditions such as a resistive load and
a current load. No matter what the
load is, the optimum operating
point in terms of maximizing the
output power is at a half of VMAX, as
shown in Figure 4(b) and (c). In case
of a resistive load, one can maximize the output power with designing RPMP matched with RL , which is
so-called impedance matching
(5)

R PMP = R L .

In case of a current load IL , one can
maximize the output power when

IOUT

VIN

VOUT

IIN

RPMP = N/(fC)
IOUT

1:N + 1
+
-

VIN

(6)

Note that maximizing the output
power under a given output voltage
is equivalent to maximizing the output current at that output voltage.
Equations (4)-(6) are independent of
a type of charge pump topology as
far as the I OUT -VOUT characteristic is
expressed by the same form.
It is beneficial to look at the
relationships between POUT, PIN, and
power efficiency h in the ideal case
in another view point. The left-most
column of Figure 4(d) shows IOUT,
VOUT, and POUT, and the center column shows IIN, VIN, and PIN as a function of VOUT. Because IOUT and VOUT are
linear lines, POUT is a second-order

VMAX = (N + 1) VIN

IIN
IIN = (N + 1) IOUT

(4)

+
-

CPMP
~NC/3

VOUT

PIN = VIN IIN = (N+1) VIN IOUT = VMAX IOUT
POUT = VOUTIOUT
η = POUT/PIN = VOUT/VMAX
(a)

(b)

VMAX

η = POUT/PIN

PIN = POUT + PLOSS

η = VOUT/VMAX

VMAX

(c)

U
O

η
1

As

IOUT
VOUT

ses

rea

Inc

V

RPMP

T

PLOSS
VOUT

POUT
IOUT

VOUT

POUT_MAX

VMAX
(d)

(e)

FIGURE 3: An (a), (b) equivalent circuit and (c)-(e) POUT, PIN, and h in the ideal case.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

85
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
