Current Load Resistive Load IOUT VOUT CP IOUT = (VMAX-VOUT)/RPMP VOUT CP IL RL VOUT IOUT POUT IOUT VMAX IL 2RPMP POUT = VOUT IOUT = VOUT(VMAX-VOUT )/RPMP VOUT VOUT VMAX/2 VMAX/2 VMAX (c) VOUT VOUT VMAX VMAX × VOUT ÷ VIN VMAX PIN VOUT η 100% VOUT VMAX POUT = 2IL POUT IIN VOUT η PIN VOUT↑ 50% 1 VOUT VMAX/2 RPMP (b) IIN = (N + 1) IOUT × VMAX/2 (Impedance Match) (a) IOUT VOUT VMAX RPMP = RL POUT_MAX = VMAX2/4RPMP at VOUT = VMAX/2 IL VOUT VOUT VMAX VMAX VMAX (d) POUT 0% POUT_MAX (e) FIGURE 4: Peak power and power efficiency in an ideal case. Intrinsic Term IIN = Parasitic Cap Term IOUT VIN VOUT IIN = N + 1b IOUT + a 1 + αT 1 = VIN η VOUT N + αT C S P R I N G 2 0 16 Φ α a T + αB b fNCVIN 1 + αT α a1 + α + 1b + a T 1 + αT T + αB b FIGURE 5: Power efficiency in a real case. 86 C IEEE SOLID-STATE CIRCUITS MAGAZINE fNCVIN IOUT αB C X N (7) (8) function with concave up, where POUT becomes maximum at the center point. IIN is proportional to IOUT as discussed in Figure 3(a). VIN is a constant across VOUT. Therefore, PIN is a monotonic function as VOUT. The power efficiency h is calculated by POUT divided by PIN, as shown by the right-most column of Figure 4(d). The common factor of IOUT is canceled out, which results in h being the linear function of VOUT. Ideally, at VOUT = VMAX, h could be 100% while IOUT = 0. When VOUT is swept, h versus POUT is described in Figure 4(e).