IEEE Solid-State Circuits Magazine - Spring 2016 - 87

Equivalent Circuit
of Real Charge Pump

Power Efficiency
of Real Charge Pump
Figure 7(a) explains how design parameters need to be updated starting from
the ideal case where a B = VTH = 0. You
want to keep IOUT-VOUT. N would need
to be increased as VTH is increased to
keep VMAX. Then, C would also need to
be increased to keep RPMP. Because IIN is
approximately proportional to N for a
charge pump with large N, IIN increases
as VTH whereas IOUT is kept the same.
As a result, h decreases. Even if an
increase in VTH is not too large to
increase N, C needs to be increased
to keep IOUT at VOUT of interest. That
increases the parasitic term of IIN in (7),
resulting in a decrease in h. Similarly,
an increase in a B increases the parasitic term of IIN, resulting in a decrease
in h. Larger a T requires larger N to
keep VMAX and RPMP. As a result, an
increase in aT can decrease h as well.

VIN

CPMP
~(1+αT)NC/3

GIN

IOUT =

IOUT

+
-

1:M
+
-

N
(1+αT)fc

RPMP =

VD = (N + 1)VT RPMP

IIN

fC (1+αT)
N

a N
1+αT

+
-

VOUT

(9)

+ 1b VIN - (N + 1)VT -VOUT

FIGURE 6: An equivalent circuit in a real case.

IOUT
RPMP =

VTH ↑

N
(1+αT)fc

N ↑(to Keep VMAX)
C ↑(to Keep RPMP)

IIN = (N + 1) IOUT + fαB NCVIN
(When αT Is Neglected)
N + 1bV - (N + 1)V
N & C & α B↑
IIN ↑ η ↓
VMAX = a
IN
T
1 + αT
(a)
VOUT

IOUT

IIN = IIN(IOUT,
αT, αB, VTH > 0)

POUT

IIN

VOUT

×

VOUT

VMAX

×

VIN

VOUT

VOUT

VMAX

÷

VMAX

PIN

VOUT

VOUT
VMAX

POUT

PIN

1

VOUT
(b)

Ideal
Real

η
VOUT

VOUT

VMAX

VMAX

VMAX

N

C

αT

αB

VTH

7

10 pF

0

0

0V

10

13.4 pF

0.1

0.1

0.5 V

100

Power Efficiency (%)

What is the impact of parasitic components on the charge pump characteristics in the actual case where
there is a finite parasitic capacitance
at the top and bottom plate of capacitors including clock drivers and a
finite threshold voltage of switching
devices? Figure 5 explains how IIN is
given by IOUT [22]. IIN has two components: intrinsic and parasitic capacitance terms. The intrinsic term is a
function of IOUT, N, and a T whereas
the loss term includes a T C, a B C, N,
VIN, and f, where a T and a B are the
top and bottom plate parasitic capacitance ratio to the pump capacitor.
Note that a B C needs to include the
gate and junction capacitance of the
driver for pump capacitors. Power
efficiency h is then expressed by a
ratio of POUT to P IN as described in (8).
Figure 6 describes an equivalent
circuit in the real case. Conversion
ratio M, output impedance RPMP, and
effective load capacitance CPMP are
updated to include a T over the ideal
case shown in Figure 3(b). GIN shows
the switching loss proportional to
the operating frequency. For a light
load with I OUT " 0, GIN degrades h.

αT
N
+ 1b
+ αBb fNC M = a
GIN = a
1 + αT
1 + αT

80

Ideal

PC

60
PD

40

VOUT ↑

Real

PB

20
0

PA

Pout
(c)

FIGURE 7: (a) VOUT versus IOUT, (b) VOUT versus h , and (c) POUT versus h in a real case.

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

87
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
