IEEE Solid-State Circuits Magazine - Spring 2016 - 88

N = 7 Vt = 0 V αB = 0
N = 7 Vt = 0 V αB = 0.1
N = 10 Vt = 0.5 VαB = 0.1

60

= 0 & VTH = 0

(#2)

40

20

(#1)

1.E-05

VTH
20

10

(#3)
0.E+00
-0.2 -0.1

0
10
Vout (V)
(a)

15

20

N = 10, C = 10 pF, aT = 0.05, Vt0 = 0 V
Vin = 0.4 V, Vout = 1.2 V
3.E-05
30
Iout
eta
2.E-05

20

Iout (A)

(#4)
(#5)

10

1.E-05

0

0.1

0.2
0.3
aB (a.u.)
(c)

0.4

0
0.1
Vth(V)
(b)

0.2

0.3

0

N = 10, C = 10 pF, aB = 0.2, Vt0 = 0 V
Vin = 0.4 V, Vout = 1.2 V
3.E-05
30

0

Iout
eta
20

2.E-05
Iout (A)

5

Power Efficiency, eta (%)

0

0.E+00

Iout
eta

2.E-05

(#6)

1.E-05

0.E+00

0

0.1

0.2
0.3
aT (a.u.)
(d)

10

0.4

Power Efficiency, eta (%)

αB

Iout (A)

Power Efficiency (%)

Ideal w/αB

80

Power Efficiency, eta (%)

N = 10, C = 10 pF, aT = aB = 0.01,
Vin = 0.4 V, Vout = 1.2 V
3.E-05
30

VIN = 2.0 V, VOUT = 12 V, f = 10 MHz, C = 10 pF
100

0

FIGURE 8: A case study on power efficiency in a real case.

TAble 1. OPTImIzATIONs Of The chArge PUmP.
PArAmeTer fOr OPTImIzATION
#

Tr/Area

1

✓

2

IOUT/Area

PIN/IOUT

clOck freqUeNcy

refereNce

Given

[17]

Given

[18]

✓

Given

[19], [20]

✓

Given

[20]

✓

[21]

✓

[22]

✓

3
4

✓

5

✓

6

✓

✓

Figure 7(b) shows how power
efficiency is affected by the parasitic
components. The curves in blue and
black show the real and ideal cases,
respectively. IIN in the real case is

88

S P R I N G 2 0 16

steeper and larger than that in the
ideal case. Especially, I IN becomes
finite at VMAX in the real case
whereas it is zero in the ideal case.
As a result, the slope of h -VOUT curve

IEEE SOLID-STATE CIRCUITS MAGAZINE

becomes gentler to the maximum
power point. To be worse, h is significantly degraded in a range of
a higher VOUT or a lower I OUT due
to the impact of nonideal device
parameters. Figure 7(c) compares h
of a real case with that of an ideal
case where VIN is 2.0 V and f is 10
MHz. The graph is drawn by sweeping VOUT. N and C are determined in
such a way that POUT hits the same
maximum value at VOUT = 12 V. However, power efficiency is decreased
from 50% at PA to 30% at PB and from
80% at PC to 40% at PD with nonideal
device parameters even though POUT
is the same value at PA and PB and at
PC and PD.



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016

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