IEEE Solid-State Circuits Magazine - Spring 2016 - 90

Power NMIN = 5
Power NMIN = 20
Area
Rise Time

Normalized Parameters

2
1.8
1.6

Definition of NMIN:
VPP = (NMIN + 1)VIN
e.g.,
αT = 0.05,
αB = 0.1,
VTH = 0

1.4
1.2
1

the option (#2). One can specify the
number of stages to be 40% larger
than NMIN, which is the minimum
number of stages to barely generate a
finite IOUT at VOUT = VPP [17]. C is calculated by a given area and a number of
stages of NOPT.

#2: Optimization to
Maximize IOUT/Area

NOPT = (1.6~1.7) × NMIN

0.8
1

1.5

2
2.5
ε = N/NMIN

3

Area, Rise Time, Power < 1.1 × (Best Case)
FIGURE 12: An optimum number of stages in ssl [20].

IOUT

IOUT

First Approximation
Real Behavior

5

IOUT

Frequency (MHz)

25 100

Once the operation frequency is
determined, one may want to design
the charge pump to have a minimal
area to output a target current at a
target output voltage (VPP). One can
draw the I-V curves with a different
number of stages where the total
capacitor area is constant as shown
in Figure 10. In other words, the
question is what number of stages
can maximize the output current
at VOUT = VPP. You already know the
answer, which is twice as large as
N MIN where I OUT is maximum [18], as
given in Figure 4.

#3: Optimization to
Minimize PIN/IOUT

Time

Time

TC /2 = 100 ns
(5 MHz)

20 ns
(25 MHz)

Time
5 ns
(100 MHz)

(a)
Under a Given Silicon Area

Relative
Transistor Area ↓

Higher Optimum
Frequency
Smaller αT
Iout at 15 v (A)

2.0E-04

Capacitor

X2
X3

1.5E-04
1.0E-04
5.0E-05
0.0E+00

Transistor

X4
X1

0 10 20 30 40 50
Clock Frequency (MHz)

Optimum C/SW Ratio and
Frequency for Maximizing IOUT
(b)

FIGURE 13: switching resistance aware optimization [21]. (a) Optimum clock frequency in a
given technology and (b) optimization of frequency and area ratio of pump cap to switching
circuit to maximize IOUT [21].

it with one-third of the total pump capacitance connected with the output
terminal. Using this model, one can

90

S P R I N G 2 0 16

find the optimum number of stages
that have the minimum rise time at a
given output voltage VPP, in this case,

IEEE SOLID-STATE CIRCUITS MAGAZINE

Another optimization is minimizing
PIN under a condition that IOUT at a certain VOUT is constrained [19], [20]. It
is found that NP_OPT described in Figure 11 provides an optimum number
of stages under a finite VTH, a T , and
a B [20]. Figure 11 shows the optimum
number of stages normalized by NMIN,
where NMIN is the minimum number
of stages to barely generate VOUT. For
example, NP_OPT/NMIN is about 1.4 when
a T = 0.05, a B = 0.1, and VTH = 0.
Let's consider the monotonic increase in NP_OPT as a function of a B,
as shown in Figure 11. Because N
and C need to be chosen to meet the
target IOUT-VOUT, a larger value of N
requires a smaller value of C. When
a B increases, an increase in the parasitic capacitance term of IIN in (7) is
mitigated with a larger N because NC
can decrease. By selecting a larger
value of N for a larger a B, a decrease
in the parasitic capacitance term of
IIN can be larger than an increase in
the intrinsic term. As a result, the
net input power can be reduced with
a larger N as a B increases.
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016
