IEEE Solid-State Circuits Magazine - Spring 2016 - 91

#4: Optimization to Make a Balance
Between Area, Power, and Rise Time
Figure 12 summarizes how area,
power, and rise time vary as the number of stages increases [20]. Each performance metric is normalized by its
own minimal value. When one selects
the number of stages 1.4 times as
large as the minimum number of
stages, the power and the rise time
can be minimal whereas the required
area is 25% larger than the minimal.
When one selects the number of
stages 2.0 times as large as the minimum number of stages, the area can
be minimal whereas the power and
the rise time are 20% and 15% larger
than their minimal values, respectively. On the other hand, when one
selects the number of stages 1.6-1.7
times as large as the minimum number of stages, all the area, power, and
rise time can be no larger by 10% than
their minimal values.

#5: Optimization of Frequency and
Area to Maximize IOUT/Area

All of the previously mentioned
optimizations are made under the
assumption that the clock frequency

is given and is at SSL. To increase IOUT
per area, the frequency must be one
of the control parameters [21]. When
the clock frequency is low enough,
the output current is proportional
to the clock frequency. Figure 13(a)
indicates that the output charge per
a half period may never be affected
when the clock frequency is slower
than 5 MHz at a certain technology
node because there is no current at
100 ns. When the clock frequency
increases to 25 MHz, the current at 20
ns is finite. One can guess that you
may never gain the output current
with a faster clock than 25 MHz. At
100 MHz, there may be little chance
to transfer any charge. As a result,
the frequency versus output current
curve could be a quadratic function
around the peak in a real pump as
shown in Figure 13(a).
Assume that the total area for the
charge pump is given and you are
asked to maximize the output current. You have a design space with
respect to the switching transistor
and capacitor area ratio. When the
transistor area is much smaller than
the capacitor area, as shown in the

left most of Figure 13(b), you would
need to run the pump at a slow clock.
The opposite extreme is the case
where the transistor area is much
larger than the capacitor area, as
shown in the middle of Figure 13(b).
You could run the pump very fast, but
you may see a large voltage loss due
to a larger parasitic capacitance associated with the transistor. By varying
the transistor-to-capacitor area ratio,
you can draw IOUT over the clock frequency as shown in the right-most
part of Figure 13(b). The graph determines the optimum clock frequency
and the transistor-to-capacitor area
ratio at the same time. In this example, the optimum point is at a relative
area marked by X2 and about 35 MHz.

#6: Comprehensive Optimum
Design with Respect to
Frequency, Area, and Power
In addition to IOUT, power efficiency
needs to be considered as well [22].
Figure 14(a) demonstrates h versus
IOUT under various switch-to-pump
capacitor area ratios and various
clock frequencies where the total
pump stage area and the number

Optimum C/SW Ratio per Frequency
for Maximizing Both IOUT and η
0.4

0.4

Model 12.5 MHz
Model 25 MHz
Model 50 MHz
SPICE 12.5 MHz
SPICE 25 MHz
SPICE 50 MHz

0.2

0.1

0.3

0.2
8 stg
10 stg

0.1

12 stg
14 stg

0.0
0.E+00

0.0
1.E-04
Iout (A)

2.E-04

(a)

3
Area (a.u.)

(b)
Area

1 (Min.)

20%

100 M-Hz

700 Ω

2.5

30% (Close to Peak)

25 M-Hz

2k-Ω

IEEE SOLID-STATE CIRCUITS MAGAZINE

S P R I N G 2 0 16

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016