IEEE Solid-State Circuits Magazine - Spring 2016 - 92

of stages are kept constant. A very
interesting observation about Fig-
ure 14(a) is that there is the optimum
point where both h and IOUT are at
maximum for each frequency. When
the area ratio of pump capacitor to
switching circuit is large, the pump
is in a state where the charge trans-
fer is incomplete under a given fre-
quency. As a result, IOUT is relatively
small. When N and f are given, the
relationship between h and IOUT in (8)
suggests that h is a function of IOUT
mainly because C is a weak function
of the area ratio and the contribution
of a B and a T is minor. Therefore, h
is also relatively small when IOUT is
small. As the area ratio decreases,
a larger amount of charges can be
transferred in a half clock period.
As a result, IOUT increases, thereby
h also increases through the sec-
ond term of (8). Thus, it is easy to
determine the optimum area ratio
by clock frequency, at which both
IOUT and h are maximized. Then, the
required total pump area is calcu-
lated to output a targeted IOUT.
This procedure is repeated for
various stages to determine the
maximum h per area, as shown in
Figure 14(b). You can select the best
point on the curves. In this example,
you may want to select the design
parameters to prioritize either area
or power efficiency, as shown in Fig-
ure 14(c), or to have moderate area
and power efficiency between the
two extreme cases.
In this Part 2, we reviewed the struc-
ture of integrated switching devices
and capacitors, an equivalent circuit
and power efficiency of the charge
pump, and several design optimiza-
tions. In Part 3, we will review state of
the art of switching circuits and appli-
cations of charge pumps.

References

[1] T. Tanzawa, "Innovation of switched-
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2016.
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IEEE SOLID-STATE CIRCUITS MAGAZINE

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About the Author
Toru Tanzawa (toru.tanzawa.jp@ieee.
org) is a distinguished member of tech-
nical staff at Micron Memory Japan,
Inc. He received the Ph.D. degree in
electrical engineering from The Uni-
versity of Tokyo, Japan, in 2002. He
has been with Toshiba and Micron,
where he has worked on the circuit
design of high-density NAND flash,
high-speed, low-voltage NOR flash,
and RF-CMOS wireless ICs since 1992.
He holds 177 granted U.S. patents,
has published 40 papers in IEEE con-
ferences and journals, and wrote the
book On-Chip High-Voltage Generator
Design: Design Methodology for Charge
Pumps, second edition (Springer, 2015)
and "Chapter 3: Low Power Memory
Design" in Power Aware Design Methodologies (Kluwer Academic, 2002). He
is a Fellow of the IEEE with a citation
of contributions to integrated high-
voltage circuits.



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