IEEE Solid-State Circuits Magazine - Spring 2016 - 99

Abstract
This talk presents a design of an energy-efficient microprocessor that
implements several techniques for operation in a very wide voltage range. A
particular implementation is based on
an open Berkeley RISC-V architecture.
To enable agile dynamic voltage and

frequency scaling with high-energy
efficiency, the design implements an integrated switched-capacitor dc-dc converter. A custom-designed SRAM-based
cache operates in a wide 0.45-1 V supply range. Techniques that enable lowvoltage SRAM operation include 8T
cells, assist techniques, and differen-

tial read. Architectural resiliency techniques include the use of error correction and dynamic column redundancy.
The processor is implemented by using an agile design methodology.
-Nagi Naganathan
SSCS Chair,
IEEE Princeton/Central Jersey Section

SSCS-Singapore Chapter Welcomes DL Lecturer Prof. Willy Sansen

T

The IEEE Solid-State Circuits Society
(SSCS) Singapore Chapter, together
with A*STAR Institute of Microelectronics (IME), jointly organized
a Distinguished Lecture, "Analog
Design in Future Nanometre CMOS
Technologies," by Prof. Willy Sansen from KU Leuven, Belgium. The
lecture was held on 17 November
2015 at IME, attended by over 50 students, researchers, and engineers
from academia and industry.
Prof. Sansen presented the analog design challenges and opportunities driven
by the era of the Internet of Things and
Digital Object Identifier 10.1109/MSSC.2016.2546581
Date of publication: 21 June 2016

Prof. Willy Sansen presents his lecture.

the advanced technology node down to
7-nm CMOS. The BSIM6/EKV model was
introduced to better capture the transistor model biased in deep weak inversion region. The rational choices of MOS
transistor W/L and biasing point for
both low-power and high-speed applica-

tions were derived based on the fT·gm/IDS
figure of merit. Moreover, the low-power
design techniques such as gain boosting, negative resistors, and bootstrapping were highlighted by Prof. Sansen to
be particularly useful for small channel
length. The advantages and limitations
of SOI FinFET and FD-SOI CMOS, the
alternatives to planar CMOS for channel length smaller than 20 nm, were
also discussed. Toward the end of the
lecture, questions from the audience on
the current gain of BJT, the vertical FETs,
and mismatch issues were answered by
Prof. Sansen.
-Tony Kim
SSCS-Singapore Chapter Chair

The attendees of the talk on 17 November 2015 pose with Prof. Willy Sansen.

IEEE SOLID-STATE CIRCUITS MAGAZINE

s p r i n g 2 0 16

99



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Spring 2016

IEEE Solid-State Circuits Magazine - Spring 2016 - Cover1
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IEEE Solid-State Circuits Magazine - Spring 2016 - Cover3
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