IEEE Solid-State Circuits Magazine - Spring 2017 - 18

every path to compare with the transis-
tor and logic schematics.

Breadboard
While the design was in layout, Nadia
Sachs translated the logic drawings
into a 7400 series transistor-transis-
tor logic IC design. This breadboard
system consisted of a rack of five
large wire wrap boards and could
execute DSP1 code in real time. We
built three of these systems: one
for a customer, one to prototype our
code for the DTMF receiver, and a
third to prove in the production test
program. Our experience in debug-
ging this system was helpful in
developing strategies for diagnosing
errors that were discovered in the
first chips.

Silicon Testing and Debugging
Layout was completed in April 1979.
A month later, the first silicon was
nonfunctional due to a mask error,
but the second attempt tested in July
was a partial success. A problem
with the reset logic was discovered.
The Allentown team bypassed this
circuit in a few packaged devices by
adding a wire from the pin to a test
pad in the middle of the chip! Six
partially functioning devices were
sent to system customers. The third
silicon in October was completely
functional. (See Figure 4.)
During this period, I fielded calls
from system customers who reported
problems. I used our development
system to verify the problem, simplify
the test, and form a hypothesis for the
error mechanism. The new tests were
applied to the test set in Allentown to
pinpoint the error.

Figure 4: A DSP1 packaged device.

18

S p r i n g 2 0 17

Development Tools
As the logic design progressed, ano-
ther team in Holmdel, New Jersey,
worked on hardware and software
development tools. An assembler
and simulator were written in C run-
ning on the UNIX operating system.
There was no need for a high-level
language compiler since the real-
time requirements and performance
limited the typical program size to
about 200 instructions.
A hardware development sys-
tem called DSPMATE was created to
allow system designers to debug DSP
code in real time while attached to
the user's system through a 40-pin
dual in-line package (DIP) plug. The
system supported breakpoints on
various data and I/O conditions.
Another smaller board (DSP emula-
tor) consisted of a DSP and external
erasable programmable read-only
memory with a 40-pin DIP connec-
tor. Many of these systems were
manufactured for our internal cus-
tomers as well as for several univer-
sity engineering programs.

Production and Beyond
By October, 1980, we sampled over
30 internal system customers with
DSP1 devices. System designers had,
for the first time, a low-cost digital
signal processing platform for cre-
ating applications that was flexible,
scalable, and reduced the time to
market. The device was widely used
in Bell Labs research and acceler-
ated the transfer of new algorithms
in speech and signal processing to
practical applications.
In 1982, we produced a second-
generation device in 2.75-µm NMOS
technology. This device was twice
as fast as the DSP1 and reduced the
amount of power needed by about
30 % . In 198 4, we developed t he
world's first 32-b floating point DSP.
The cost and power requirements
for the early generations of DSPs lim-
ited them to telecom infrastructure
applications. The fourth generation,
DSP16 in 1986, was our first proces-
sor in CMOS technology. We developed
a DSP core methodology from this

IEEE SOLID-STATE CIRCUITS MAGAZINE

architecture that we could easily use in
low-cost application-specific products
(systems on a chip). For the first time,
digital signal processing was practical
for consumer applications: modems,
answering machines, cordless phones,
and cell phones.
The success of this ground-
breaking development was due to
the leadership and vision of Dan
Stanzione and John Thompson as
well as the work of many talented
engineers in Holmdel and Allen-
town. I am fortunate to have been
given the opportunity to contribute
to the project and work for a com-
pany that had such great synergy
between research, development and
manufacturing.

Reference

[1] J. R. Boddie, G. T. Daryanani, I. I. Eldu-
miati, R. N. Gadenz, J. S. Thompson, S.
M. Walters, and R. A. Pederson, "A digital
signal processor for telecommunications
applications," in Tech. Dig. 1980 ISSCC,
pp. 44-45.

About the Author
James B o ddie (jrboddie@gmail
.com), now retired, worked for 25 years
in the field of digital signal process-
ing technology development for Bell
Laboratories, AT&T Microelectronics,
Lucent Technologies, and Agere Sys-
tems. He contributed to the birth of
six generations of DSP architectures,
hardware and software development
tools, and application software. He
managed DSP R&D in these companies
as the technology evolved from gen-
eral purpose single-chip processors
to application-specific systems on a
chip. He was an executive director at
Agere Systems and led the StarCore
design center, a joint venture with
Motorola. He received the Ph.D. degree
in electrical engineering from Auburn
University in 1976 and the electrical
engineering and master of science
degrees from the Massachusetts Insti-
tute of Technology in 1973. He holds
three patents in digital signal process-
ing architecture and is the author of
17 papers. He is a Bell Labs fellow and
received the 1988 IEEE Morris N. Lieb-
mann and the AT&T Patent Awards.



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