IEEE Solid-State Circuits Magazine - Summer 2014 - 76
NIkOLIc´ NOVI saD stats
70 participants
8 from industry (11.4%)
17 IEEE Members (24.2%)
39 Ph.D. students (55%)
12 undergraduate students (17%)
10 academic staff (14.2%)
IN a secOND stOp IN serBIa, NIkOLIc´ aDDresses at MINI cOLLOqUIUM OrGaNIZeD BY ssc/eD
serBIa aND MONteNeGrO at the 29th INterNatIONaL cONFereNce ON MIcrOeLectrONIcs (MIeL 2014)
While visiting Serbia, SSCS DL Borivoje Nikolic´ participated in a MinColloquia on Nanotechnologies and Nanodevices, which was organized
by the ED/SSC Serbia and Montenegro Chapter.
Held on Monday, 12 May 2014, at the Serbian Academy of Sciences
and Arts in Belgrade, this event drew about 60 people who heard Prof.
Nikolic´'s lecture, "Circuit Design in Nanoscale FDSOI Technologies."
abstract
Planar fully depleted SOI technology with ultrathin body and buried oxide
presents a platform for an energy-efficient design in deeply scaled technologies without major changes in the bulk-CMOS design infrastructure.
Good control of short-channel effects with a thin transistor body offers a
possibility to reduce the supply voltage. Thin buried oxide provides threshold tuning via body bias. Overall design optimality is achieved through
sensitivity-based optimization by selecting optimal supplies and thresholds.
Detailed information on the event can be found at http://miel.elfak.
ni.ac.rs/Mini_coloquia_on.htm.
-Ninoslav Stojadinovic´
Chair, SSCS-Serbia-Montenegro
sscs DL Borivoje Nikolic´ speaking at the Mini-colloquia on Nanotechnologies and Nanodevices organized by ssc/eD serbia Montenegro in May.
DesIGN OF aN eNerGY-eFFIcIeNt prOcessOr
WIth INteGrateD sUppLY reGULatION
abstract
This talk presents the design of an energy-efficient microprocessor that
implements many of the techniques for operation in a very wide voltage
range. A particular implementation is based on an open Berkeley RISC-V
architecture. To enable agile dynamic voltage and frequency scaling with
high energy efficiency, the design implements an integrated switchedcapacitor dc-dc converter. A custom-designed SRAM-based cache operates in a wide 0.45-1-V supply range. Techniques that enable low-voltage
SRAM operation are the use of 8T cells, assist techniques, and differential
read. The specifics of mapping the processor into 28-nm fully depleted SOI
technology are discussed as well.
-Borivoje Nikolic´,
Berkeley Wireless Research Center,
University of California, Berkeley
76
SU M M E R 2 0 14
IEEE SOLID-STATE CIRCUITS MAGAZINE
prof. Borivoje Nikolic´ delivering an Ieee DL talk at the school of
electrical engineering, University of Belgrade.
http://www.miel.elfak
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2014
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