IEEE Solid-State Circuits Magazine - Summer 2015 - 15

demonstrates the severity of the
variable on-resistance.
2) To which node(s) should the n-wells
of M 3 and M 8 in Figure 4(d) be
connected?
3) How high can VX in Figure 4(d)
go to avoid stressing M 14 ?

VDD
CK
S1

S3

S2

Y

M3

M4

P

Q
M1

Vin1

CK
S4

Vout

X

Answers to Last Issue's Questions
1) Do VP and VQ in Figure 5 reach 0 V
at the end of the regeneration phase?
Yes, they do. We observe that
M 1 -M 3 are on but with zero drain
current because both M 3 and M 6
(or M 4 and M 5 ) are off. Nodes P and
Q are therefore discharged to zero.
2) Explain why M 3 and M 4 in Figure 5
can be omitted if the inputs have
rail-to-rail swings.
With rail-to-rail input swings,
either M 1 or M 2 is off, cutting off
the path from VDD to ground. By
contrast, if | Vin1 - Vin2 | is small,
then both M 1 and M 2 remain on.
3) Explain why the coupling through
C GD7 in Figure 5 is less on the rising edge of CK than on the falling edge of CK .
On the rising edge of the clock,
M 7 begins from the off state and
its C GD is primarily due to the
gate-drain overlap capacitance.
On the falling edge, the transistor

M6

M5

CK

M2

Vin2

M7

Figure 5: The StrongARM latch.

begins in the deep triode region,
with C GD7 . C GS7 , exhibiting a
greater feedthrough.

References

[1] D. D. Russel, "Field effect switching circuit," U.S. patent 3,448,293, Oct. 7, 1966.
[2] M. Kikushi and M. Takeda, "Distortionless
switching circuit," U.S. patent 3,942,039,
May 20, 1974.
[3] G. Pollitt, "Constant impedance MOSFET
switch," U.S. patent 4,093,874, Dec. 29,
1976.
[4] B. Brandt, P. Ferguson, and M. Rebesehini,
"Analog circuit design for RT ADCs," in
Delta-Sigma Data Converters, S. Norsworthy, R. Schreier, and G. Temes, Eds. Piscataway, NJ: IEEE Press, 1997.

[5] M. Dessouky and A. Kaiser, "Input switch
configuration suitable for rail-to-rail operation of switched op amp circuits," Electron. Lett., vol. 35, pp. 8-10, Jan. 1999.
[6] A. M. Abo and P. R. Gray, "A 1.5-V 10-bit,
14.3 MS/s CMOS pipeline analog-to-digital
converter," IEEE J. Solid-State Circuits, vol.
34, pp. 599-606, May 1999.
[7] M. Dessouky and A. Kaiser, "Very lowvoltage digital audio TR modulator with
88-dB dynamic range using local switch
bootstrapping," IEEE J. Solid-State Circuits,
vol. 36, pp. 349-355, Mar. 2001.
[8] H. Wei and B. Razavi, "An 8-bit 4-GS/s 120mW CMOS ADC," IEEE J. Solid-State Circuits, vol. 349, pp. 1751-1761, Aug. 2014.
[9] J. Mathew and B. Razavi, "A 12-bit 200-MS/s 3.4mW CMOS ADC with 0.85-V supply," in Symp.
VLSI Circuits Tech. Dig., June 2015, pp. 30-31.

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IEEE SOLID-STATE CIRCUITS MAGAZINE

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2015

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