DAtA Converter ArCHIteCtures The basic algorithm used in the successive approximation (initially called feedback subtraction) ADC conversion process can be traced back to the 1500s, relating to the solution of a certain mathematical puzzle regarding the determination of an unknown weight by a minimal sequence of weighing operations [61]. The familiar electronic implementation of the successive X Test approximation ADC using the balance scale analogy is shown in Figure S4. It is interesting to note that many of the fundamental ADC architectures used today were discovered and published in one form or another by the late 1960s; these are listed in Table S1. The dates given are of first publication or patent filings, whichever occurred first. Analog Input Assume X = 45 Comparator Serial Data Output + Is X ≥ 32? Yes → Retain 32 → 1 Is X ≥ (32 + 16)? No → Reject 16 → 0 Is X ≥ (32 + 8)? Yes → Retain 8 → 1 Is X ≥ (32 + 8 + 4)? Yes → Retain 4 → 1 Is X ≥ (32 + 8 + 4 + 2)? No → Reject 2 → 0 Is X ≥ (32 + 8 + 4 + 2 + 1)? Yes → Retain 1 → 1 - Weighting Network Convert Start Control Logic Totals: X = 32 + 8 + 4 + 1 = 4510 = 1011012 (a) (b) Figure S4: A successive approximation ADC: (a) balance scale analogy and (b) electronic implementation (feedback subtraction ADC). TABLE S1. DATA CONVERTER ARCHITECTURES By DATE OF APPEARANCE. ARCHITECTURE DATE REFERENCE SAR algorithm Reeves' counting ADC Successive approximation ADC Flash or parallel ADC (electron tube coder) Tracking ADC Delta modulation and differential PCM Voltage-to-frequency converter First- and second-order loops, multibit, with oversampling with noise shaping (sigma-delta, but without the digital part) Bit-per-stage ADC (binary and Gray) Subranging ADC Dual-slope ADC Multibit sigma-delta implementation Sigma-delta ADC (first use of the name) Folding ADC (Gray code) Subranging ADC with error correction (redundancy) Pipelined ADC with error correction (redundancy) Triple-slope ADC Complete sigma-delta ADC with digital filtering Generalized pipelined architecture Quad-slope ADC Continuous time sigma-delta Bandpass sigma-delta 1500s 1939 1947 1948 1950 1950 1952 1954 [61] [26] [29] [31] [62] [63] [64] [65] 1956 1956 1957 1961 1962 1962 1964 1966 1967 1969 1971 1973 1976 1988 [66] [67] [68] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79] IEEE SOLID-STATE CIRCUITS MAGAZINE su m m E r 2 0 15 27