IEEE Solid-State Circuits Magazine - Summer 2015 - 40
Digital
Display
12
14
Floating
dc
Supply
10
Comparison
Amplifier
DAC
Clamping
Relay
Relay
Control
Circuit
20
Analog Voltage
Input
Negate
Comparison
22
16
Clock Pulse
Generator
18
Figure 2: A patent showing a SAR ADC.
VREF
3VREF
4
Vin
VREF
2
>
VREF
2
Vin
VREF
4
<
0
VREF
2
>
3VREF
4
<
3VREF
4
>
VREF
4
<
VREF
4
t
(a)
(b)
Figure 3: (a) A search for analog estimates; (b) decision-directed binary search.
To overcome this difficulty, we
modify the MDAC operation to
f (Vin, VREF) = 2Vin - VREF
if Vin 2 VREF
2
= 2Vin if Vin 1 VREF .
2
(1)
(2)
Figure 5(a) plots Vres = f (Vin, VREF) .
As shown in Figure 5(b), the implementation compares Vin with VREF /2
before residue generation, directing
the left plate of C 2 to VREF or 0 accordingly. In this case, the capacitors
and the comparator sample the input simultaneously. Since the circuit
40
su m m E r 2 0 15
does not employ a main sample-andhold (SHA), it is also called a "SHAless" front end.
The foregoing principle readily
lends itself to pipelining: while one
MDAC stage is in the amplification
mode, the next can be in the acquisition mode and vice versa [Figure 5(c)].
The concurrent operation of the
MDAC stages means that the conversion speed is limited by only the
acquisition and amplification times of
one stage, typically the first one.
The compact implementation along
with pipelining makes this "1-bit/
stage" architecture an efficient solution,
IEEE SOLID-STATE CIRCUITS MAGAZINE
especially for resolutions not achievable by flash topologies (approximately 8 bits and above).
This architecture entails five sources of inaccuracy: kT/C and op-amp
noise, capacitor mismatch, finite opamp gain, op-amp nonlinearity, and
comparator offset. Of these, noise
directly trades with power dissipation, capacitor and op-amp imperfections can be calibrated in the digital
domain, and comparator offset is
accommodated by a simple modification described below. High-speed
designs must also cope with the mismatch between the sampling instants
of the capacitors and the comparator
in Figure 5(b).
One may surmise that the hardware and power dissipation of the
above architecture grow linearly
with the resolution; for each additional bit, we can simply add one
more MDAC stage to the end of the
pipeline. Today's designs, however,
are noise-limited, requiring that,
for one more bit, the front-end
stage (and possibly the subsequent
stages) incorporate proportionally
larger capacitors and higher op-amp
bias currents. In other words, the
hardware and power of the overall
pipeline grow approximately exponentially with the resolution.
1.5-Bit/Stage Architecture
Let us return to the sources of error.
It can be proved that capacitor mismatch and finite op-amp gain alter
the slope of the residue plot [Figure
6(a)], whereas comparator offset,
VOS, shifts the decision point away
from Vin = VREF /2 [Figure 6(b)]. Both
cases may exhibit a residue "overrange," but the former introduces an
error in Vres even outside the overrange regions. We deal with the latter
case in this section, modifying the
architecture so as to tolerate large
comparator offsets.
Our subsequent study is more
easily followed if we consider a
fully-differential system, one wherein
the differential input voltage can
vary from - VREF to + VREF . The residue plot of Figure 5(a) is redrawn
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2015
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