C1 C1 2Vin - VREF X - Vin X Vout + C2 - C2 VREF Vout + t Figure 4: The MDAC implementation. Vres VREF EF in 2V 2V in - VR C1 X Vin - C1 X Vout + Vin VREF VREF 2 (a) C2 - C2 Vin Vout + VREF 2 VREF 2 VREF CK Stage 1 (b) C1 Amplification Mode Acquisition Mode Stage 2 C1 C2 Vin - - + + Vout C2 VREF 2 VREF 2 VREF (c) Figure 5: (a) A residue plot, (b) use of a comparator to generate proper residue, and (c) two pipelined stages. in Figure 7(a) for such a system and expressed as f (Vin, ! VREF) = 2Vin - VREF Vin 2 0 (3) = 2Vin + V REF Vin 1 0. Vres Vres C2 > C1 VOS (4) Note that the comparator now compares Vin with zero. For example, if Vin = 0 but the comparator interprets it to be Vin = + 2 mV, then the Overrange Overrange V REF VREF VREF 2 VREF (a) Vin VREF 2 (b) VREF Vin Figure 6: The effect of (a) capacitor mismatch and (b) finite op-amp gain on the residue. IEEE SOLID-STATE CIRCUITS MAGAZINE su m m e r 2 0 15 41