IEEE Solid-State Circuits Magazine - Summer 2015 - 44
stage (with no matching required
between the capacitors in one stage
and those in the next). Thus, highresolution SAR ADCs tend to occupy
a large area if the DAC unit capacitor
size is dictated by matching requirements rather than by kT/C noise.
Third, the lack of residue amplification means that the comparator
input noise can limit the performance, as is typical for resolutions
of 8 bits and above. A low-noise
comparator's response time and
power dissipation can far exceed
those of a standard design.
Pipelined and SAR architectures
also share some issues: the matching
of the capacitors must be commensurate with the resolution unless
digital calibration is employed, and
the circuit generating VREF must
exhibit fast settling and low noise.
Logic
Vin
VDAC1
VDAC2
VDAC3
DAC1
DAC2
DAC3
Register
Register
Register
Figure 11: Simple 2-bit/cycle SAR ADC.
response time, t comp, the logic
delay, t logic, and the settling of the
DAC, t DAC . In the 1-bit/cycle architecture studied thus far, one conversion period is approximately
equal to N (t comp + t logic + t DAC) . For
a given CMOS technology node,
each of these three components
has a lower bound regardless of (or
weakly dependent on) the power
dissipation, thereby limiting the
ADC's speed.
Second, the SAR ADC imposes
on its DAC both a high accuracy
and a high resolution. For example,
a 10-bit design requires 1,024 unit
capacitors, or 2,048 if the system
is fully differential. By comparison,
the pipelined topology of Figure 5(c)
incorporates only two capacitors per
SAR Speed Improvement
The conversion speed of SAR ADCs
can be improved through the use of
various techniques [16]-[24]. Three
are described here.
The first and most obvious approach
is to interleave two or more channels
and proportionally raise the conversion
rate. The generic interleaving issues
apply here as well, including area and
input capacitance penalty and the problem of interchannel mismatches. Also
Pipelined and SAR ADC architectures
date back to the mid-1900s.
32
32
31
33
28
24
VDAC (LSB)
VDAC (LSB)
Vin1 = 23.5 LSB
16
24
25
23
21
18
16
15
Vin1 = 12.5 LSB
8
8
t1
t2
t
t1
t2
(a)
Figure 12: (a) SAR response with incomplete DAC settling and (b) use of redundancy to correct the error.
44
s u m m E r 2 0 15
IEEE SOLID-STATE CIRCUITS MAGAZINE
t3
(b)
t
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