IEEE Solid-State Circuits Magazine - Summer 2015 - 63

Architectural Trends
As speculated above, at least part of
the progress seen over the years has
certainly been due to pure process
technology scaling. However, scaling
alone would not have been sufficient.
As we shall discuss in this section,
there were a number of innovations
in circuit and architecture design
that not only made further scaling
possible, but led to new topologies
that made better use of scaled transistors. With this relentless and concurrent optimization involving technology, circuits, and architectures, it
is not surprising that we have seen
increasing competition among previously disjoint ADC options.
While it was relatively straightforward to make architectural decisions
in the past, today's ADC designer is
confronted with an overlapping design
space offering multiple solutions that
are difficult to differentiate in their

suitability. For example, the design
space for pipelined ADCs has been
encroached on by time-interleaved SAR
converters. Similarly, wideband deltasigma converters such as [42] now offer
bandwidths that were previously only
achievable with Nyquist converters.
Figure 6 gives an indication of
architectural trends. As is commonly
known, the SAR topology continues to
be actively researched and conforms
to the general trend toward minimalistic, op-amp-less architectures. In
order to extract high speed from the
SAR topology, time interleaving is typically needed. This explains, in part,
an up-tick in the number of reported
designs that use time interleaving,
illustrated in Figure 7. More generally,
this trend is, of course, also supported
by the increasing integration density
available in silicon, which has also
enabled multicore microprocessors.

SAR ADCs
The SAR ADCs discussed in the literature in recent years show great versatility and range from ultralow-power
to ultrahigh-speed designs (using time
interleaving). To see this, contrast the
10-bit 200 kS/s converter of [43] with
the 8-bit 90 GS/s part of [39]; both use
very similar circuitry in their converter

core. Somewhere in between, we see
10-bit 2.6 GS/s time-interleaved SAR
ADCs that can digitize the entire cable
TV spectrum [44], as well as highly efficient 100-MS/s, 11-ENOB converters
[45] that meet the demands of typical
wireless receivers. While much of the
progress in SAR converters is enabled
by technology scaling, there have been
a number of important circuit and architecture innovations as well. These
include the combination of SAR conversion with pipelining [46] and the
use of dynamic residue amplification
in such hybrid topologies [45]. Other
recent advancements include the judicious use of redundancy and digital-toanalog converter (DAC) replica timing
[47], majority voting for noise reduction [48], and integrated buffering to
ease the input drive requirements [49].

Pipelined ADCs
Challenged by the impressive energy
efficiency and scaling robustness of SAR
converters, the designers of pipelined
ADCs have continued their search for
op-amp-less residue amplification techniques. We have seen intriguing innovations in fully-dynamic amplification
[50], ring-amplifier-based amplification
[51], [52], and comparator-based amplification [53], as well as bucket-brigade

40
35
30

Other
Flash
Pipe
∆Σ
SAR

25
Count

reached in about 11 years, assuming
that we can maintain the progress
rate of 1 dB per year.
To extract the rate at which the
high-frequency asymptote of Figure 3
moves to the right, we use FOMS =
150 dB as an arbitrary reference point
and measure (for each year) up to which
conversion rate this level of efficiency
is maintained. This yields the plot of
Figure 5, from which we observe doubling every 1.8 years, or 60x every ten
years. A good portion of this progress
slope can be explained by technology
scaling. The transit frequency of CMOS
transistors has improved by about a
factor of ten over the last decade. This
leaves about a factor of six that was
likely gained by "clever design."
Note that the above number
quantifies the rate of power efficiency improvement for high-speed
designs, and it is therefore not surprising that the improvement rate is
quite similar to that of FoMW. Lastly,
note that since the low- and high-frequency asymptotes in Figure 3 shift
at different rates, the corner shifts
to the right over time. While it was
located at about 1.4 MHz in 1997, the
roll-off now occurs at about 42 MHz.

20
15
10
5
0

2000

2005
Year

2010

2015

Figure 6: Architectures of ADCs described in the literature (ISSCC 1997-2015 and VLSI
Circuits Symposium 1997-2014).

IEEE SOLID-STATE CIRCUITS MAGAZINE

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