IEEE Solid-State Circuits Magazine - Summer 2015 - 76

ANALOG VERSUS DIGITAL POWER CONSUMPTION
was identified, with analog implementation benefits for systems with
low-to-medium range signal-to-noise ratio (SNR) requirements (up
to about 10 effective number of bits). Since this study, digital power
consumption has benefited more profoundly
from silicon technology scaling. However, in the
context of feature-extracting ADCs, the power
consumption of the analog analytics benefits in
a similar way from technology scaling due to
improved digital enhancement techniques (see
the section "Implementation Challenges and
R
Opportunities for Feature-Extracting ADCs")
N
S
: P ~ log 2
nalytics
A
l
and dynamic feature selection. As a result, the
a
it
ig
D
cross-over point between analog and digital
Scaling
Technology
does not seem to be shifted drastically in adR
N
~S
vanced CMOS technologies (Figure S4). Low-to:P
ics
t
medium range SNR processing, as required in
y
al
An
typical classifying sensor interfaces, still benefits
g
Run-Time Dynamic
alo
from analog analytics.
An
Power-Accuracy
A second important observation, is that
Scalability
Digital Calibration
the analog power consumption scales much
Feature Selection
better (proportional) with the precision
Required
requirements, than its digital counterpart
0
10
20
30
40
50
60
70
80
Output SNR
(logarithmic). This illustrate an additional
opportunity for analog analytics: dynamic
Figure S4: Analog and digital power consumption trends in relation to required SNR.
accuracy-power scalability.
1/f Limited Based on Devoted Area

Power Consumption

Vittoz, and later Sarpeshkar, analyzed the power consumption footprint of analog and digital processing systems [27] [28]. A clear
cross-over point between analog and digital power consumption

processing prior to digitization. Analog circuits are constrained by noise
and accuracy requirements that do not
necessarily benefit from voltage scaling and in most cases suffer from lower
supply voltages [34]. The key parameters for a robust analog design are in

as well as operating condition and
process variations. This becomes
more challenging in finer geometry
process nodes, which increasingly
suffer from reduced matching quality
for minimum feature size transistors
and shrinking of voltage headroom.

A feature-extracting ADC can exploit
power-accuracy scalability along two axes.
broad categories of design parameters
such as transistor geometries, process
manufacturing parameters, and operational parameters such as temperature
[35]. In a typical high-performance analog
design, traditionally a combination of
meticulous layout and floor planning,
careful circuit topologies such as fully
differential architectures and accurate
device modelling are critical to ensure
robustness against device mismatch

76

su m m e r 2 0 15

This problem is aggravated when on
tries to introduce more flexible programmability into the analog analytics blocks, requiring more transistor
stacking and operational robustness
across multiple circuit configurations.
Combatting these impairments in the
traditional way could seriously compromise power efficiency and/or die
size, or otherwise result in additional
distortion to the computed features.

IEEE SOLID-STATE CIRCUITS MAGAZINE

Digital Enhancement Techniques
in Feature-Extracting ADCs
To mitigate some undesirable attributes of deep submicron technology nodes for robust analog design,
active and passive components
matching using digitally assisted
techniques have increasingly been
used in various analog circuits.
Data converters, in particular, have
extensively benefited from background and foreground digital calibration and compensation [35] for
various reasons: affordability in
cost, die area, and power, as well
as the availability of digital gates
for mixed signal design in deep
submicron technologies, which has
promoted the application of digital
compensation in data converters.
Most common approaches to digital
calibration, specifically in data converters as described in [34], involve
tightly coupled closed-loop digital
calibration [see Figure 8(a)] that in
most cases utilizes the embedded



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