IEEE Solid-State Circuits Magazine - Summer 2016 - 35
Most importantly, when needed, [Mark] gave
critical autonomy to the graduate students
who made up the design team.
instead of the hardwired implementation that DASH used.
By creating a custom and flexible
substrate for multiprocessing, FLASH
could offer an integrated and streamlined set of hardware primitives for
both global cache coherence and also
user-level message passing. It was, in
effect, the ideal research vehicle to test
and compare both type of systems.
FLASH was an enormous research
success, spanning over five years of
development and graduating more
than 20 Ph.D. and M.S. students, and
Mark was the primary faculty member
behind it. He helped to guide major
architectural and design decisions of
the node controller (nicknamed the
MAGIC chip), and he steered the team
not only in creating a useful simulation
framework to estimate its performance
but also in using those results to capture the key research questions FLASH
needed to answer. Of course, with any
group of bright-eyed graduate students,
there is always the danger of over-scoping the problem, and Mark played a
critical role in containing the untrained
appetites of the team to ensure that the
machine would be buildable. But perhaps most importantly, when needed,
he gave critical autonomy to the graduate students who made up the design
team. Led primarily by Jeff Kuskin
and Dave Ofelt, along with a talented
team of other doctoral candidates, the
team exemplified learning by doing, all
under Mark's mentoring.
As with any large-scale system,
there were efforts down in the silicon,
with Mark teaching the team to build a
custom six-ported memory whose area
and frequency was critical to the node
controller's performance. He helped
tackle computer-aided design (CAD)
issues in finding out what new tools were
being developed, either in the commercial space or internal to companies,
and how to get access to those tools
for his students. He worked to get large
100
Energy Operation
(Nomalized for technology)
coherent-and whether a scalable
cache-coherency system could be reasonably implemented in hardware and
run fast enough. Some argued it could
be done and that the system could
maintain a coherent shared memory
image without the programmer's help.
Others pushed for simpler distributed
machines that could only share coherency information through explicit message passing.
At Stanford, Mark worked on an early
machine, the DASH multiprocessor,
that implemented a ground-breaking 64-node machine with distributed cache-coherent shared memory
and could support several scientific
applications in the SPLASH suite of
parallel applications [12]. Two of the
faculty sponsors of DASH, Mark and
Stanford President John Hennessy,
not only guided the hardware development but also helped to facilitate
an early and highly successful technology transfer to industry. The Silicon Graphics Origin 2000 was one of
the first commercial hardware-based
cache-coherent systems, and it was
architected and built by many of the
same students who had built DASH
and were later hired by SGI. This was
an example of the general principle
articulated by computer pioneer Bert
Sutherland that "technology transfer
is a contact sport."
Almost immediately after completing DASH, Mark began the dev e lopment of the next Stanford
parallel system, called FLASH, to
explore questions around the parallel programming model and how it
related to distributed shared memory versus message passing and the
data structures and implementations on which those programming
models are built [13]. One of Mark's
observations motivating FLASH was
that ASIC development had sufficiently advanced to the point that
a reasonably complex system could
be built by a small team of motivated
graduate students. That opened the
door to build a programmable implementation of a so-called "node controller" (the engine providing the
cache coherency model primitives),
10
Energy-Efficient Frontier
1
0.00
Intel 80386
Intel Pentium III
Intel Core 2
Alpha 21064
HP PA
AMD K7
AMD Phenom
0.01
0.10
Performance (Normalized for Technology)
Intel 80486
Intel Pentium IV
Intel Xenon
Alpha 21164
Power PC
AMD Turion
Sun Super Sparc
Intel Pentium
Intel Itanium
Intel Atom
Alpha 21264
IBM-Power
AMD Thlon
Sun Ultra Sparc
1.00
Intel Pentium II
Intel Itanium D
Intel Core i7
MIPS
AMD K6
AMD Operation
FIGURE 3: a survey of microprocessors on a Pareto curve for the energy-per-operation and
performance (from [11]).
IEEE SOLID-STATE CIRCUITS MAGAZINE
su m m E r 2 0 16
35
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