IEEE Solid-State Circuits Magazine - Summer 2016 - 40

Mark encouraged a very academic-like,
innovation-driven engineering culture
within the company.

transfer control and data much more
quickly, it ended up with more than
one bit in flight at a time on the wires
and required more bandwidth than
a conventional DRAM core of the era
could supply. Given the limited pin
counts available in cheap packaging
of the 1980s, Mark and Mike chose
to use a narrow, multiplexed bus for
command, address, and data. This
allowed high bandwidth for large
transfers, at a cost of latency and efficiency for smaller transaction sizes.
To help counteract this, they envisioned a split transaction bus, with
multiple independent accesses outstanding. The DRAM devices included
delay registers, which allow the system to adjust the cycle on which data
was written or read.
Mike and Mark's original concept
was for the DRAMs to be mounted vertically to minimize propagation delay,
as shown in Figure 4. This arrangement proved impractical for a nonelectrical reason; the parts tended
to fall over during wave soldering.
Nearly all Rambus systems either soldered parts directly to the main board
or, in later years, used chip-scale
packaging on memory modules. As
packaging technology has improved,
we are seeing this same idea revisited today (rotated 90°) in the form of
a high bandwidth memory and hybrid
memory cube.

Making Rambus systems work
also required significant circuit innovations. Integrated CMOS phaselocked loops (PLLs) and delay-locked
loops DLLs for interchip communication had started appearing in the late
1980s, including Mark Johnson and
Ed Hudson's implementation for MIPS
Computer Systems' floating point
coprocessor [1]. On-chip PLLs made it
possible to deskew clock buffer delays
that formerly had to be subsumed in
the overall timing budget. Deskewing
allowed the entire interface to run
faster. Making PLLs and DLLs work
on DRAMs was challenging, however,
due to process performance limitations and continued voltage scaling. There were many generations
of improvements in these designs,
and Mark, his coworkers at Rambus,
and later his colleagues and students
at Stanford were at the forefront of
this effort. The original Rambus PLLs
contained a six-stage ring-based main
loop plus an interpolating fine loop to
provide fine control [2]. The design
used source-coupled logic, requiring
voltage headroom to operate properly. Subsequent versions adopted
DLLs for faster lock time and used
replica biasing or inverters on regulated supplies to provide better process tolerance and reduced voltage
headroom requirements. Over the
years, Mark and engineers at Rambus

17 16

15 18

Figure 4: The original vertical DRAM design for minimum delay.

su m m E r 2 0 16

IEEE SOLID-STATE CIRCUITS MAGAZINE

would pioneer many PLL innovations, especially relating to building
a stable high-speed clock on a noisy
memory substrate.
Compounding the challenges was
the speed and challenge of the DRAM
process. The focus of the DRAM industry had for years been increasing density and lowering cost. This focus had
made the DRAM process extremely
cost conscious, to the point where the
first RDRAM implementation had only
a single layer of metal with connectivity (and even the power busing!) in the
vertical direction achieved through
resistive polysilicon. Ultimately, by
the 18-Mb generation, two layers of
metal were available, but the slower
DRAM processes continued to make
the design more challenging.
The early days at Rambus gave Mike
and Mark an opportunity to innovate
on the structure of the company culture as well. Early on in the formation
of the company, they realized that they
couldn't directly build DRAMs, it made
no sense for anyone to invest the
enormous capital required to build a
new DRAM fab just to support their
new designs, and the margins on
DRAMs would not permit a "fabless" semiconductor model either.
Instead, they decided to create an IP
company, a very new idea in 1989.
In this model, the circuit and architecture ideas and the overall system,
including reference board layouts,
became the real products of the company. These would be licensed to
DRAM and system companies. Partnerships were developed with all the
major DRAM manufacturers where
Rambus would develop the I/O circuits, and the DRAM companies
would develop a compatible core.
With the interface between the two
areas of the die defined, the DRAM
manufacturers would ultimately join
the two pieces to make the masks,
process the wafers, and assemble and
test the final devices.
Mark also encouraged a very academic-like, innovation-driven engineering culture within the company,
holding a weekly "Mark's meeting"
even after returning to Stanford. At

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2016