IEEE Solid-State Circuits Magazine - Summer 2016 - 65

transistors composed of N+/P-well/
N-well/P-sub never turns on. This
allows us to use low-voltage transistors for switching devices because
any voltage difference among four
terminals of each switching transistor is not higher than 2Vin. A lowvoltage transistor can run with a high
frequency clock to reduce the area
under a given condition for the output voltage and current.
Figure 7 illustrates another topology using a two-phase clock to reduce
the number of phases for faster clocking [11]. To stabilize the potential of
each isolated N-well, decoupling capacitors are added. The rise time can be
affected, but the output current would
not, once the pump enters a steady
state, because the charging current is
not needed for the decoupling capacitors afterward. The transfer gates can
have thin gate oxide because any voltage difference between the four terminals is smaller than 2VIN. On the other
hand, the main, auxiliary, and decoupling capacitors have to have a thick
gate oxide because a voltage as high as
VOUT is applied to them.
Figure 8 is a reduced version of Figure 7 using a two-phase clock with body
effect cancelation [12]. Because the
transfer gate is connected as a diode,
the threshold voltage at VBS = 0 V(VT0)
affects the transfer efficiency. However, when transistors with low VT0 is
available, this topology may have a
lower voltage difference between the
gate and source, resulting in a lower
stress on the transistor.

φ3

- PMOS (Possibly Thin Gate Oxide)
- Isolated Nwell Per Stage
- Four-Phase Clock
- Demonstrated with VDD = 1 V

φ1
φ2
φ3
φ1

φ2

φ4

Figure 5: PMOS switching transistors.

φ4

Bloch et al. (1998)

φ3
PW0

- Isolated P-Well Per Stage

PW1

- The P-Well Is Connected to a
Node Whose Potential Is Lower
Than the Other to Fully
Avoid the Parasitic BJT Operation
(N+/Pwell/Nwell/Psub).
SW1
SW2

φ1
PW0

φ2

PW1

φ3
φ2

φ1

φ4

Figure 6: NMOS switching transistors placed in an isolated P-well per stage.

Favrat et al. (1998)
φ1

- Two Phase for Both dc-dc and ac-dc
- Four Phase/Well Potential Controlled
When the Reverse Current Is Significant

φ2

Main Stages

Reconfigurable Pump
If a system has multiple charge pumps
and if they don't run simultaneously, one
can reduce the entire pump area by
adding some switches to make pumps
reconfigurable as shown in Figure 9 [13].
PC1 is a unit pump stage, and PC2 is a
switching circuit. The switching circuit
has two capacitors, but they need not
be large because only a local boosted
potential to turn on the switching
device in triode needs to be generated. Figure 9(d) illustrates a charge
pump that has two configurations,
two arrays with two stages for each

Sawada et al. (1995)

φ4

N 1a

Auxiliary Stages
N 1b

N 1a

φ1

φ2
NW1

N 1b
φ2

φ1

NW1
CDC1
N 2a

N 2b

N 2a

φ2

φ1
NW2

NW1
N 2b
φ1

φ2

NW2
N 3a

N 3b

CDC2

NW2

Figure 7: PMOS switching transistors with an isolated N-well per stage.

IEEE SOLID-STATE CIRCUITS MAGAZINE

SU M M E R 2 0 16

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2016