IEEE Solid-State Circuits Magazine - Summer 2016 - 72

UHF (860-960 MHz)
Antenna

80 µW
3V

4m
4W

Matching
Network

Rectifying
Multiplier

Reader/
Writer

Tag
IC
Load

Figure 26: A power transceiver system for RFID.

transformers can generate sinusoidal clocks whose amplitudes become
two times or 2M times greater than
the original output voltage of energy
transducer, as shown in Figure 25,

report shows that multisine wave
improves the system's power efficiency [33]. On the other hand, there
is also theoretical discussion that a
conventional continuous wave has

High area- and power-efficient integrated
dc-dc and ac-dc voltage-up conversion with
an extremely low voltage would need further
advanced technology and design.
where M is the turn ratio of the transformer. A larger ac signal amplitude
results in a larger operation window
for the charge pump.

higher power efficiency than a multisine wave [34], [35].

System Design Challenge of RF-dc
Power Conversion

As mentioned earlier, the threshold
voltage of a switching transistor significantly affects the circuit performance of a charge pump, which is
enhanced when the input voltage is
extremely low. Tunnel FET (TFET) is
expected to have steep subthreshold
slope to work at a low voltage [36].
Because it has little leakage current
when the source voltage is higher
than the drain voltage ideally, it fits
well with the demand of an extremely
low voltage charge pump. Parasitic
capacitance per drain current will be
a key parameter for the availability
of TFET into the charge pump design.
As discussed in [2], the parasitic
capacitance of the pump capacitors
degrades the area and power efficiency of the charge pump. A fully
depleted silicon on insulator may
allow for N-well capacitors with significantly low parasitic capacitance
in comparison with the standard

Another interesting system design
area for charge pump techniques is
RF-dc power conversion for RFID, as
shown in Figure 26 [31]. The reader
and writer for RFID send a wireless
signal to a tag IC. The power and frequency of the signal are controlled
to meet the RFID specification such
as the maximum power is not higher
than 4 W and the frequency range
is a limited band width in UHF, for
example. The transmitted signal is
also used as power source for the IC.
The load power has to be maximized
as well as the output voltage is well
controlled by optimal design from
antenna to load. Therefore, designers need to effectively convert the
input power to output power including the matching network or filter
[32]. Signal shape may be another
design parameter. An experimental

SU M M E R 2 0 16

Challenges and Opportunities in
Advanced Technology

IEEE SOLID-STATE CIRCUITS MAGAZINE

CMOS. This can bring an opportunity to improve power efficiency of
charge pumps.
Clock boosting contributes to
reducing the minimum supply voltage. It has realized oscillator operation at below 10 mV with discrete
inductors [37]. Efforts to increase
the quality factor of integrated
inductors will result in reducing the
minimum supply voltage to widen
the operating window of fully integrated energy harvesters.
Thus, high area- and power-efficient integrated dc-dc and ac-dc voltage-up conversion with an extremely
low voltage would need further
advanced technology and design, as
well as ac-dc voltage-down conversion with a high conversion ratio [38]
and complete energy harvesting systems including harvester, interface
circuits, storage and application electronics [39].

References

[1] T. Tanzawa, "Innovation of switched capacitor voltage multiplier-Part 1: A brief
history," IEEE Solid-State Circuits Mag.,
vol. 8, no. 1, pp. 51-59, Jan. 2016.
[2] T. Tanzawa, "Innovation of switched capacitor voltage multiplier-Part 2: Fundamentals of charge pump," IEEE Solid-State
Circuits Mag., vol. 8, no. 2, pp. 83-92, June
2016.
[3] J. F. Dickson, "On-chip high-voltage
generation in MNOS integrated circuits
using an improved voltage multiplier
technique," IEEE J. Solid-State Circuits,
vol. SSC-11, no. 3, pp. 374-378, June
1976.
[4] J. F. Dickson, "Voltage multiplier employing clock gated transistor chain," U.S.
Patent 4,214,174, July 22, 1980.
[5] S. D'Arrigo, G. Imondi, G. Santin, M. Gill,
R. Cleavelin, S. Spaglicca, E. Tomassetti,
S. Lin, A. Nguyen, P. Shah, G. Savarese,
and D. McElroy, "A 5V-only 256k Bit CMOS
flash EEPROM," in Proc. IEEE Int. SolidState Circuits Conf. Tech. Dig., 1989, pp.
132-133.
[6] V. Dham, D. Oto, K. Gudger, K. Congwer,
Y. Hu, J. Olund, and S. Nieh, "A 5V-only
E2PROM using 1.5µ lithography, in Proc.
IEEE Int. Solid-State Circuits Conf., New
York, 1983, pp. 166-167.
[7] A. Umezawa, S. Atsumi, M. Kuriyama,
H. Banba, K. Imamiya, K. Naruke, S. Yamada, E. Obi, M. Oshikiri, T. Suzuki, and
S. Tanaka, "A 5V-only operation 0.6μm
flash EEPROM with row decoder scheme
in triple-well structure," IEEE J. SolidState Circuits, vol. 27, no. 11, pp. 1540-
1546, Nov. 1992.
[8] J. Wu and K. Chang, "MOS charge pumps
for low-voltage operation," IEEE J. SolidState Circuits, vol. 33, no. 4, pp. 592-597,
Apr. 1998.

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