IEEE Solid-State Circuits Magazine - Summer 2017 - 11

I1

I2

X
Vin1

M1
CK

M2

Vin1

Y

Vin2

Vr 1 Vr 2

M3
CK

MCK1

VCM

Vin1

(a)

M4
MCK2

Vr 1

Vin2

Vr 2
t1

t
(b)

Vr 1
Vr 2
Vin2

S1

S3
c1

Y

X
M1

A

S5
S6
S2

S4

CK

M2
MCK

B
c2
(c)

FIGURE 4: (a) A comparator input stage based on two differential pairs, (b) the effect of different CM levels, and (b) an alternative
input stage.

accurately track that of Vin1 and
Vin2. To s e e t h i s p o i n t , w e n o t e
in Figure 4(b) that, even if Vin1 Vin2 . Vr1 - Vr2 at t = t 1, each differential pair experiences a heavy
imbalance and suffers from a low
transconductance. As a result, the
mismatches at nodes X and Y a nd
beyond contribute a higher inputrefer red offset. Second, the circuit introduces four devices, M 1 -M 4
at the input and must therefore
deal with the offsets of two differential pairs. Specifically, we have
I 1 - I 2 ? (Vin1 - Vin2) - [(Vr1 - Vos1) (Vr2 - Vos2)], w h e r e Vos1 a n d Vos2
denote the offset voltages of M 1, 2 and
M 3, 4, respectively. Third, the input
CM range of the circuit has a lower
bound given by VGS1 - 4 and the voltage headroom necessary for M CK1
and M CK2. This issue limits the flash
ADC's full-scale range, especially at
low supply voltages.
Shown in Figure 4(c) is an alternative fully differential input stage that
ameliorates the foregoing difficulties. Here, a single differential pair
senses an input difference produced
by the input switching network and
given by (Vin1 - Vin2) - (Vr1 - Vr2). In
other words, this circuit performs
the subtraction in the voltage domain
[while in Figure 4(a), it is done in
the current domain]. The comparator
operates in three phases. First, CK is
low, S 1 -S 4 are on, and the input network samples the analog signal on C 1
and C 2. Next, these switches turn off
and S 5 and S 6 turn on, producing at
A and B a voltage difference nearly
equal to (Vin1 - Vin2) - (Vr1 - Vr2) . With

a slight delay, CK then goes high to
This means that the input capaciactivate the comparator core circuit.
tance in the sampling mode is more
This delay is necessary to guarantee
than five times that in Figure 4(a).
that VA - VB departs significantly
When S 5 and S 6 turn on, VAB reaches
[(Vin1 -Vin2) - (Vr1 -Vr2)] [C 1 / (C 1 +C in)]=
from zero before M 1 and M 2 begin
(5/6) [(Vin1 -Vin2)-(Vr1 -Vr2)], exhibitto amplify.
In contrast to the structure of
ing a loss of about 17%.
Figure 4(a), the input stage shown
It is possible to reduce the capaciin Figure 4(c) deals with the offset
tance presented to the analog input
of only one differential pair and
by changing the switching sequence
does not require accurate tracking
in Figure 4(c). We first turn on S 3 -S 6
between the input and reference
to sample the differential reference
CM levels. Furthermore, capacitive
on the capacitors and then turn off
coupling in this arrangement allows
these sw itches a nd t ur n on S 1
rail-to-railinputswings.
a nd S 2. The differYet another advantage
ential volta ge t hus
is that the analog samgener ated between
The principal
pling provided by C 1
A and B is the same
drawback of
and C 2 in Figure  4(c)
a s b efor e , b ut t h e
the flash ADC is
obviates the need for
capacita nce seen
the exponential
a lumped front-end
by Vin1 a nd Vin2 i s
growth of its
sampler for the ADC.
now given by the
"cost" as a
On the other hand,
series combination
function of
the clocking and X
of the input capaciresolution.
and Y discharge act o r s a n d C in. T h i s
tions in Fig ure  4(a)
approach, however,
tend to integrate the input a nd
f a c e s t w o d r a w backs: 1) C 1 and
hence "smear" the sampling point,
C 2 load the resistor ladder, causgenerally necessitating that the
ing a long settling time for Vr1 and
ADC employ an explicit sample-andVr2, and 2) the circuit no longer
hold circuit.
samples the analog input, requirThe use of the sampling network
ing a front-end sampler for the
in Figure 4(c) does raise the input
ADC. A similar timing is described
capacitance presented to the analog
in [6].
input. To ensure negligible attenuation of (Vin1 - Vin2) - (Vr1 - Vr2), C 1
Flash ADC Variants
and C 2 must be chosen much greater
A number of architecture and cirthan the capacitances seen at A and B.
cuit techniques have been invented
For example, suppose C 1 = C 2 = 5C in,
to ease the tradeoffs in flash stages.
where C in includes the gate capaciWe study two here.
tance of the differential pair and
Recall that the input capacitance
the drain capacitance of S 3 (or S 4 ).
of the converter grows rapidly with

IEEE SOLID-STATE CIRCUITS MAGAZINE

SU M M E R 2 0 17

11



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2017

IEEE Solid-State Circuits Magazine - Summer 2017 - Cover1
IEEE Solid-State Circuits Magazine - Summer 2017 - Cover2
IEEE Solid-State Circuits Magazine - Summer 2017 - 1
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IEEE Solid-State Circuits Magazine - Summer 2017 - Cover3
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