IEEE Solid-State Circuits Magazine - Summer 2017 - 12

X2

Vin
Vr 2

X2
A2

Vr 2

A2

Latch

Latch

Y2

X1

VX 1
X1
A1

Vr 1

Latch
Y2

VY 2

VY 1

Latch

Vr 1

VX 2

(a)

Latch
Y1

Vin

Vr 1 Vm Vr 2

Y1

A1

(b)

Latch
(c)

FIGURE 5: (a) A flash stage showing comparators' input differential pairs, (b) characteristics provided by the differential pairs, and (c) a flash
stage using interpolation.

+

VF

+

Vin

+

VF -VF-
Flash
ADC

-

Vin

+

CK1

-

Vin-Vin

-

VF

CK2
(a)

(b)

FIGURE 6: (a) A flash stage preceded by a polarity detector and (b) the resulting characteristic.

+

VREF Vin

+

Pipelined ADC

VREF Vin

SAR ADC

Vres

SAR
Logic

-

-

VREF

VREF
(a)

(b)
Flash
ADC

X(s)

Y(s)

DAC
(c)

FIGURE 7: The use of flash stages in (a) pipelined converters, (b) SAR ADCs, and (c) DR modulators.

12

SU M M E R 2 0 17

IEEE SOLID-STATE CIRCUITS MAGAZINE

the resolution. It is possible to alleviate this issue through the use of
interpolation. In this context, we view
each comparator as a differential
pair followed by a latch. Let us first
examine the differential pair outputs in Figure 5(a) as Vin varies from
below Vr1 to above Vr2 . Noting that
VX1 = VY1 for Vin = Vr1 and VX2 = VY2
for Vin = Vr2, we can construct the
characteristics shown in Figure 5(b).
Now, we recognize that VX1 = VY2
at Vin = Vm = (Vr1 + Vr2) /2. That is, a
latch sensing these two voltages (or
VY1 and VX2 ) can detect when Vin crosses
midway between Vr1 and Vr2 . As
depicted in Figure 5(c), the "interpolating" flash [7] architecture doubles
the resolution without doubling the
number of differential pairs.
The performance improvement
afforded by interpolation appears
almost free, but it does require that
the comparators include a differential pair and suffer from its power
dissipation. In particular, a simple
StrongArm latch would not suffice
for the comparator design in this
environment.
Another approach to reducing the
complexity and power is illustrated
in Figure 6(a) [8]. Here, a front-end
comparator detects, under the command of CK 1, the polarity of V +in - V -in
and accordingly routes the inputs
through two of the switches such
that the flash stage always senses a
positive differential value. Plotted in
Figure 6(b), the resulting characteristic



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2017

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