IEEE Solid-State Circuits Magazine - Summer 2017 - 19

OFF

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State 1

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Increasingly Negative Signal

Increasingly Positive Signal

OFF

Differential
Voltage
Across Load
Current
Class D Response with Zero Input

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(b)

State 4

Decreasingly Positive Signal

Decreasingly Negative Signal
(a)

FIGURE 12: (a) A BD/filterless modulation scheme and (b) BD/filterless waveforms.

from the switching driver on performance. The target dynamic range is
120 dB. The digital PWM modulator
should be carefully designed, and
the analog noise from clock jitter
supply should be analyzed and modeled. Of course, digital implementation can offer low quiescent current
consumption and there is no need
for an analog DAC.
Digital quantization noise is suppressed by the fourth-order digital
PWM (Figure 14). The design of the
digital PWM follows three major
considerations. The first is the spectral shaping of the pulse and timing
errors to enhance dynamic range.
The second is to maximize the input
range for which the modulator is stable. The third is to reduce the switching rate as much as possible. The
modulator topology is the cascadeof-integrators with feedback and
the two local resonators providing
in-band nulls for the optimal noise
suppression. The multiple feedback
signals from the output are 1 b. The
fourth-order noise transfer function has two zeros at 5 and 18 kHz

implemented with two local resonators in the modulator loop.
Increasing the modulator order
beyond the fourth order does not
significantly enhance the quantization noise performance but, rather,
decreases the maximum input range for
which the modulator is stable. Increasing the ratio of fs/fosc improves pulsewidth resolution and thus reduces
quantization noise. However, the modulator consumes more dynamic power
with a higher fs. The lower limit of the
switching rate fosc is restricted by
the unity-gain frequency of the loop
transfer function. Specifically, the
switching rate should not be lower than
r times the unity-gain frequency of
the loop transfer function. Otherwise,

Digital
Input

+
-

the rate of change of the comparator
input signal can exceed the rate of
change of the triangle waveform and
can saturate the modulator. In this
design, the switching rate of the triangle waveform is slightly higher than
r times the unity-gain frequency of
the loop transfer function. Further
reduction of the switching rate either
compromises the stability margin or
must be accommodated by reducing
the bandwidth of the modulator loop,
which degrades the spectral shaping.
Nonlinearity of the driver switch,
as shown in Figure 15, also impacts
the class D driver performance. The
finite on-resistance of the driver
switch can cause nonlinearity and
degrades the power efficiency. The

Digital
Loop
Filter

Switching
Driver
fosc

Digital PWM

fs
Analog

FIGURE 13: A digital PWM class D amplifier.

IEEE SOLID-STATE CIRCUITS MAGAZINE

SU M M E R 2 0 17

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Summer 2017