IEEE Solid-State Circuits Magazine - Winter 2014 - 41

600

500

400

300

200

100

0
Industry + Non-European
Univ/Research

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012
140

159

155

115

128

138

134

154

164

153

113

143

139

Europractice Research

105

Europractice Academic

313

281

237

200

234

243

215

298

285

305

337

322

301

FIGURE 2: Breakdown of designs fabricated by the eURoPRActIce MPW service.

be from one vendor, while for other
projects a flow based on best-in-class
design tools from multiple vendors
may be required. At the smallest
geometry IC processes, the design
flow is often defined by the foundry,
e.g., TSMC, but the rich set of design
tools available means that these specific design flows are available and
supported. In addition, a wide range
of tools not dedicated to IC fabrication
are now part of the portfolio including, for example, high-level system
design, PCB layout and analysis, and
device modeling (technology CAD).

IC Design
The aim has always been to stimulate
the adoption of new techniques and
technologies. Initially, this was done
by making integrated flows available
and using MPWs to reduce fabrication
costs. With more advanced technologies, additional stimulation activities
were required. For deep submicron
(DSM) technologies of 90-nm and
below, the high cost of manufacture
was a barrier for many academic institutions. Even after making the best use

of MPW techniques and after a silicon
subsidy from the EC was applied, the
cost was still unaffordable for many
projects. Aware that the technical
demand was there and that price was a
problem, EUROPRACTICE was obliged
to solve this problem. The solution
was to subdivide the minimum block
size offered by the foundry and allow
academic institutions to buy one or
more subblocks, as shown in Figure 1.
After introducing this program in
2003, known as "mini@sic," there was
a distinct increase in the number of
designs submitted for technologies
where mini@sic was available.
After the introduction of the mini@
sic program, it became clear that some
academic institutions were still unable
to contemplate designing with these
DSM technologies. The reason cited
was a lack of training on the specific
techniques of designing at or below 90
nm. This was tackled by the EC training action IDESA, which gave practical tutorials illustrating DSM design
methodology using design tools and
technologies from the EUROPRACTICE portfolio. This tightly coupled

training action was only possible due
to the commonality of tools and design
kits within the academic institutions
across Europe. A breakdown showing
the designs fabricated over the last
decade is shown in Figure 2.
The early MPW runs featured
large numbers of digital circuits, but
by 1994 a new platform for digital
design was beginning to emerge, the
programmable device. At first these
programmable devices, whose design
software typically ran on low-cost
PCs rather than the relatively expensive UNIX workstations associated
with ASIC design tools, were seen as
a replacement for university tutorial sessions that had traditionally
employed breadboards, with perhaps
the possibility of some small student
projects using the largest available
devices. EUROCHIP introduced design
software and hardware from the programmable device vendors Altera
and Xilinx to the portfolio and also
introduced a wider range of PC-based
third-party design tools to allow the
fullest possible exploitation of this
programmable device technology.

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Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2014