IEEE Solid-State Circuits Magazine - Winter 2014 - 6

a ssoc iate editor's vie w

Marcel Pelgrom

Living in an Uncertain World

Every quarter there is at least one
pundit telling us that Moore's law
will end. Writing about the upcoming
expiration of a 1970s prediction is of
more interest to columnists than the
majority of microelectronics engineers. Probably nobody will notice
when the last stage of the famous
prediction of transistor count doubling every 18-24 months becomes a
reality in 2020 or in 2022, or 15 years
from now, or with the 7-nm lithography node or the next financial crisis.
Moore's law will never die; my
prediction is that it will just fade
away as its improvement rate decays
over the next decades.
At every IEDM, technologists will
continue showing yet another process
improvement and the public relations
department of the respective company will take care of the rest. The
signs are there already: From the 180nm node onward, the strict coupling
between the node name, the half pitch
of the essential layers, the minimum
lithography line width, and the minimum effective gate length was abandoned. In a 20-nm design-rule manual
you will hardly find a 20-nm width
or spacing. As transistor density was
boosted via more wiring layers, larger
dies, more densely packed memory,
etc., Moore's law survived. Not to
speak of other forms of stretching
the argument by three-dimensional
devices, by stacked structures, or by
simply rephrasing it to an economical
nanodollar per transistor relation.
Generations of designers lived
in the predictable world of Moore's
law. Yet major changes are at hand.
Digital Object Identifier 10.1109/MSSC.2013.2289587
Date of publication: 30 January 2014

w i n t e r 2 0 14

The certainty of continuous process improvement is rapidly being
overtaken by the ultimate consequence of scaling: reaching the stochastic disorder at the atomic level.
The number of ions in crucial parts of
devices is evolving from a big-number
continuum into a small unpredictable discrete quantity. Moreover, tremendous improvements in accurately
controlling the global parameters
in standard IC manufacturing have
tended to cause the statistical properties of devices to dominate the design
choices in many design disciplines.
Designers and layout engineers
that grew up with rigorous processvoltage-temperature analysis are now
confronted with equally designed
devices that behave like tickets in a
raffle. Their replica-biasing strategies, layout symmetries, differential structures, and other ingenious
tricks that rely on the equality of
devices produced side by side are
now obsolete. Poorly educated in statistical methodologies, they are not
used to estimating variances, crosscorrelations, rank-linear analysis, etc.
Monte Carlo does not trigger dreams
of Mediterranean villages but horrifying scenarios of weekend-long
simulations of a mere hundred-transistor-count circuit.
Young engineers see a glimpse of
the statistical framework during their
electrical engineering (EE) education.
Next to some probability density
functions, they are fiddling around
with formulas without really understanding the world behind them.
Correlation is introduced to connect
everything to everything else, with
nothing forcing them to examine the
underlying mechanisms.

IEEE SOLID-STATE CIRCUITS MAGAZINE

Is there one university requiring
practical statistical work for a B.E.E.
degree? Teaching students to deal with
nonidealities during data collection
and with the tedious process of data
analysis, with the many pitfalls and
the (un)certainty of any conclusion?
Yet, there are many areas on the
horizon where this part of education will pay off. Statistical variation
between device parameters has been
known for decades. But the diverse
range of methods to work around
these issues raises worries whether
the stochastic background is really
understood. Most on-the-fly methods
use the timing schedule as an escape.
But in ever-higher speed and bandwidth systems enabled by advanced
technologies, the next actors in the
statistical drama enter the stage: jitter,
bit-error rates, and synchronization.
An examination of the database on
analog-to-digital conversion papers
(maintained by Prof. Boris Murmann
at Stanford) shows that the jitter limit
is holding at approximately 0.5 ps,
with no significant progress for more
than a decade. Is this a fundamental
barrier in physics or the inability to
think in statistical solutions? Bit-error
rates and synchronization problems
play a fundamental role, yet the lack
of significant progress in practical
applications does worry. Similar to the
techniques employed for accessing
and dealing with mismatching components, new techniques for battling
time variance will have to be invented.
Without breaking the statistical
spell, a major deferral in IC performance improvement is as certain as
the next pundit predicting the end of
Moore's law.

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2014