IEEE Solid-State Circuits Magazine - Winter 2014 - 63

DL Michael H. Perrott Speaks on System-Level Simulation of TimeBased Circuits and Digital PLLs at SSCS Lehigh Valley

Dr. Michael H. Perrott of Silicon Laboratories, Nashua, New Hampshire,
presented twin talks to the Lehigh Valley (LHV) Chapter of SSCS on 24 October 2013 that were of special interest
to its cadre of former Bell Laboratories IC designers and CAD tool developers with extensive phase-locked
loop and/or CAD design experience.
The program, which LHV Chapter Chair Robert Peruzzi dubbed "a
great double-header," attracted at
least three IEEE Fellows, including
LHV Vice-Chair Paul Davis, as well
as student members from Lehigh
University. "It was a roaring success," said LHV Chapter Treasurer
Roger Minear. "It's been a long time
since I've seen so many folks paying
very close attention to talks with a
lot of of new technical content."
Dr. Perrott's first paper, "Fast and
Accurate System Level Simulation of
Time-Based Circuits Using CppSim and
VppSim," described two simulators
capable of analyzing circuits characterized by a mixture of C++ and Verilog models that have been developed
by Dr. Perrott as part of his research
efforts over the past 12 years. Aside
from providing fast and accurate
simulation of mixed-signal circuits in
which time is a key signal domain, the
freely available tools avoid the high
cost of licensed simulation software.
A constant time step approach
provides a seamless connection
between C++ and Verilog models. A
"double_interp" protocol is used to
keep track of edge timing information
and also provides accurate calculation
of the impact of the edge transitions
of binary-valued signals on analog
blocks. This protocol greatly speeds
up the computer analysis of mixedsignal circuits where edge timing

information plays an important role
and enables accurate calculation of
sensitive analog quantities such as
edge jitter.
CppSim, with C++ as the simulation engine, is most efficient for
system simulations focusing on analog performance with digital support. VppSim, using Verilog as the
simulation engine, is most efficient
when simulations focus on digital
verification with C++ analog blocks or
stimulus. This hybrid approach is particularly valuable for mixed-signal circuits where the key analog variables

are the time positions of the edges of
binary-valued signals. A software simulation of a PLL locking, which ran in
about 10 s, was included.
These freely downloadable tools,
with supporting tutorials, publications, and application examples, may
be found at www.cppsim.com.
A second talk on PLLs, "High-Performance Digital Fractional-N Frequency Synthesizers," began with
a review of well-established PLL
topologies using an analog charge
pump, loop filter, and oscillator
frequency control and focused on

DL Michael perrott (center) with LhV-sscs chapter officers (from left): paul Davis, roger
Minear, robert peruzzi, and richard Booth

Digital Object Identifier 10.1109/MSSC.2013.2289645
Date of publication: 30 January 2014

addressing members of the LhV-sscs chapter on pLLs and caD tools.

IEEE SOLID-STATE CIRCUITS MAGAZINE

w i n t e r 2 0 14

http://www.cppsim.com

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2014