IEEE Solid-State Circuits Magazine - Winter 2014 - 68
the CAE simulation tool to predict
mechanical, thermal, and electrical properties, enabling the buildin of manufacturability, reliability,
and performance in the early stage
of product development. CAE
approaches thus allow accelerated
learning and competitive time to
market. He shared examples and a
case study in this talk.
-Boon Leng Lim
Chair, SSCS-Penang
DL Quartet Presents Technical Program
at Second Meeting of SSCS-Poland
F
Four IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturers
(DLs) visited the AGH University of
Science Technology (UST) in Cracow,
Poland, to participate in the second
meeting of the SSCS Poland Chapter
on 30 September 2013. The meeting,
which was opened by Chapter Chair
Prof. Pawel Grybos, Prof. Tomasz
Szmuc, vice rector of the AGH-UST,
and Prof. Maciej Ogorzalek, chair of
the IEEE Poland Section, drew about
50 attendees including researchers,
Ph.D. and M.S.C. students from several universities in Poland. Talks in
the morning were by
■ Stefan Rusu (Intel Corporation),
"Microprocessor Design in the
Nanoscale Era"
■ Franz Dielacher (Infineon Technologies), "Circuit Design in SiGe:
C for Microwave Links and Active
Safety Systems"
■ Lucien Breems (NXP Semiconductors), "Wideband Delta-Sigma
Modulators"
■ Jan Craninckx (IMEC), "Low-Power
Successive Approximation ADCs for
Wireless Applications" (the abstract
published in Fall 2013 issue).
They provided the opportunity
for young researchers and students
to discuss the latest trends and
developments in microelectronics and were the perfect occasion
to promote the IEEE and invite new
members to join SSCS-Poland. A lab
demo was organized in the afternoon in cooperation with the IEEE
Student Branch AGH-UST on noise
Digital Object Identifier 10.1109/MSSC.2013.2295746
Date of publication: 30 January 2014
68
w i n t e r 2 0 14
(From left) sscs DLs stefan rusu, Franz Dielacher, Lucien Breems, and Jan craninckx lecturing at
the second chapter meeting of sscs-poland.
a lab demo on noise minimization in integrated circuits.
the DLs together with the sscs-poland chapter members.
optimization of integrated circuits
in cadence environment. Because
of the students' great interest in the
subjects and countless questions
IEEE SOLID-STATE CIRCUITS MAGAZINE
from the audience, the meeting did
not finish until late in the evening.
-Pawel Grybos
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2014
IEEE Solid-State Circuits Magazine - Winter 2014 - Cover1
IEEE Solid-State Circuits Magazine - Winter 2014 - Cover2
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IEEE Solid-State Circuits Magazine - Winter 2014 - Cover3
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