IEEE Solid-State Circuits Magazine - Winter 2015 - 16
Annually, the ten technical subcommittees of ISSCC
update their analysis of industry trends for the
benefit of the community at large.
1.E+05
ISSCC 1997-2014
VLSI 1997-2014
Energy (fJ/conv-Step)
1.E+04
Delta-Sigma 2015
Pipeline 2015
1.E+03
SAR 2015
Envelope
1.E+02
1.E+01
1.E+00
1.E-01
1.E+04 1.E+05 1.E+06 1.E+07 1.E+08 1.E+09 1.E+10 1.E+11
fsnyq (Hz)
Figure 3: The reported ADC energy use per conversion step plotted against Nyquist frequency.
1.E+11
1.E+10
Bandwidth (Hz)
1.E+09
1.E+08
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
10
20
30
40
50
60
70
80
90
100
SNDR (dB)
ISSCC 1997-2014
VLSI 1997-2014
Jitter = 1 psrms
Jitter = 0.1 psrms
Delta-Sigma 2015
Pipeline 2015
SAR 2015
Figure 4: The ADC bandwidth (Nyquist frequency) plotted against SNDR.
16
W I N T E R 2 0 15
IEEE SOLID-STATE CIRCUITS MAGAZINE
110
120
Data Converters
Subcommittee Chair:
Boris Murmann, Stanford University,
Stanford, California, USA
Data converters serve as key building blocks in virtually all electronic
systems and bridge the analog physical world to the digital circuitry
dominant in modern ICs. Key metrics, such as linearity, bandwidth,
and power efficiency, continue to be
the dominant drivers for innovation,
as evidenced by the data converters presented at ISSCC 2015. Also,
for the first time, we see a converter
in 14-nm FinFET technology. This
design leverages the integration density of this technology to realize a
process-voltage-temperature
(PVT)
tolerant time-to-digital converter
using 214 delay elements.
Figure 2 shows an overview of analog-to-digital converter (ADC) power
efficiency expressed as power dissipated relative to the effective Nyquist rate (P/fsnyq) and as a function
of signal-to-noise and distortion ratio
(SNDR). For low-to-medium-resolution converters, energy is primarily
expended to quantize the signal; the
overall efficiency of this operation
is typically measured by the energy
consumed per conversion and quantization step. The dashed trend-line
represents a benchmark of 5-fJ/
conversion-step. Higher-resolution
converters face the additional burden of overcoming circuit noise, necessitating a different benchmark
proportional to the square of signalto-noise ratio, represented by the
solid line. Contributions at ISSCC
2015 are highlighted by the colored squares representing various
converter architectures, and contributions from previous years are
marked by smaller markers. DeltaSigma, pipeline, and successive approximation register ADCs at various
SNDR design points continue to push
the limits of energy efficiency. (Note
that on this chart, a lower P/fsnyq
metric represents greater efficiency.)
Figures 3 and 4 also show overviews
of the reported ADC energy use per
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2015
IEEE Solid-State Circuits Magazine - Winter 2015 - Cover1
IEEE Solid-State Circuits Magazine - Winter 2015 - Cover2
IEEE Solid-State Circuits Magazine - Winter 2015 - 1
IEEE Solid-State Circuits Magazine - Winter 2015 - 2
IEEE Solid-State Circuits Magazine - Winter 2015 - 3
IEEE Solid-State Circuits Magazine - Winter 2015 - 4
IEEE Solid-State Circuits Magazine - Winter 2015 - 5
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IEEE Solid-State Circuits Magazine - Winter 2015 - Cover3
IEEE Solid-State Circuits Magazine - Winter 2015 - Cover4
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