IEEE Solid-State Circuits Magazine - Winter 2015 - 20
ISSCC 2015 showcases novel circuit and system
solutions that open new vistas for society.
next generation of low-power and
high-performance computing systems. Figure 13 summarizes trends
in data rates for various communication channels.
Digital Systems-
Energy-Efficient Digital
Subcommittee Chair:
Stephen Kosonocky, AMD,
Fort Collins, Colorado, USA
The demand for ubiquitous mobile
functionality to achieve enhanced
productivity, a better social-networking experience, and improved multimedia quality continues to drive
innovation in SoCs, which are also
constrained by a need to improve
battery life and reduce cost. While
the performance of embedded application processors has increased to
meet the rising demands of generalpurpose computing, dedicated multimedia accelerators are necessary to
provide dramatic improvements in
performance and energy efficiency
for emerging applications. At the
other side of the spectrum, sensor
nodes for the IoT require low-energy
wireless and sufficient computational capabilities.
Technology scaling continues to be
exploited to deliver designs capable
4.0
MCUs
8b
3.6
3.2
16 b
MIPS/mW
2.8
32 b
Digital Systems-
High-Performance Digital
2.4
2.0
1.6
Subcommittee Chair: Stefan Rusu,
Intel, Santa Clara, California, USA
1.2
The relentless march of process technology brings more integration and
energy-efficient performance to mainframes, enterprise, and cloud servers.
At ISSCC 2015, superlatives abound:
IBM details its high-frequency eightcore, 16-thread System z mainframe
0.8
0.4
0.0
1998 2000 2002 2004 2006 2008 2010 2012 2014
Year
Figure 14: The evolution of energy efficiency in commercial microcontrollers.
Energy-Efficient Technologies Used in Commercial MCUs
+
LP and LL
Technologies
Architecture and
Accelerators
Power
Gating
Integrated Variation
Compensation
PMU
Aggressive
VDD Scaling
Memory in
Logic
20
14
20
12
20
10
20
00
Nonvolatile
Memory
ULP and ULL
Technology
Figure 15: Energy-efficiency techniques exploited in microcontroller design.
20
W I N T E R 2 0 15
IEEE SOLID-STATE CIRCUITS MAGAZINE
20
15
90 nm
CMOS
Scaling
of operating at lower voltages, resulting in reduced energy per operation,
as well as lowering the area required
to implement specific functions. Processors that will be unveiled at ISSCC
2015 are built in a variety of technology nodes, with best-in-class results
accomplished with higher integration, and improved performance per
watt as seen in Figure 14. These are
demonstrated in various process
nodes ranging from 130- to 14-nm
FinFET, as well as low-power FD-SOI
CMOS technologies.
Semiconductor chips used for the
IoT and other embedded application
areas demand energy-efficient active
operation while also requiring ultralow power state retention to enable
event-driven operation with fast
wake up. Typically, an energy-efficient MCU is used as the main processing element for local processing
and system control of these applications. Over time, the microcontroller
energy efficiency, shown in Figure 15,
has continuously improved through
a combination of technology and
design techniques.
Current R&D Thrusts
Real-Time Clock
Integrated Energy
Always-On Harvestning
Peripherals
Dynamic
Scalability
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2015
IEEE Solid-State Circuits Magazine - Winter 2015 - Cover1
IEEE Solid-State Circuits Magazine - Winter 2015 - Cover2
IEEE Solid-State Circuits Magazine - Winter 2015 - 1
IEEE Solid-State Circuits Magazine - Winter 2015 - 2
IEEE Solid-State Circuits Magazine - Winter 2015 - 3
IEEE Solid-State Circuits Magazine - Winter 2015 - 4
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IEEE Solid-State Circuits Magazine - Winter 2015 - 6
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IEEE Solid-State Circuits Magazine - Winter 2015 - Cover3
IEEE Solid-State Circuits Magazine - Winter 2015 - Cover4
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