IEEE Solid-State Circuits Magazine - Winter 2015 - 21

Chip Complexity
10,000
5.6 Billion!
Transistor Count (Millions)

1,000

100

1
1992 1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016
Year

Figure 16: Transistor count versus year.

0.999

1.00

1.20

0.525

1.00

0.346 0.90

0.85
0.242
0.80
0.75
0.171
0.127
0.60
0.0920.081
0.073

0.100

0.050

Digital Systems-Memory
Subcommittee Chair:
Joo Sun Choi, Samsung Electronics,
Hwasung, Korea
Mobile products are everyone's companion and need to store and process ever-increasing amounts of
data. Progress is possible only by
constant improvements in area, power, and performance of volatile and
nonvolatile memory (NVM). FinFET
technology is now mainstream for
embedded SRAM and DRAM, facilitating continued scaling. Improvements
in DRAM data rates support the increasing demands of greater data
volumes. NAND flash memories have
moved from 2 b/cell to 3 b/cell, and
3-D multilayer designs are now typical. Embedded flash, which is essential to IoT and wearable applications,
has moved to 28 nm. Among emerging memories, STT-MRAM is the most
mature, although ReRAM is quickly
catching up.

VMIN (V)

1.000

Bit Size (µm2)

processor in 22-nm SOI with 64 MB
of eDRAM L3 cache and 4-MB/core
eDRAM L2 cache. Oracle details its
SPARC M7 processor with 32 S4 cores,
a 1.6-TB/s bandwidth 64-MB L3 cache,
and a 0.5-TB/s data bandwidth onchip network to deliver more than
three times the throughput compared
to its predecessor. It also includes 280
SerDes lanes that support up to 18-Gb/s
line rate and 1-TB/s total bandwidth. Intel details its next-generation Xeon processor, which supports 18 dual-threaded 64-b Haswell cores, 45-MB L3 cache,
4 DDR4-2133MHz memory channels,
40 8-GT/s PCIe lanes, and 60 9.6-GT/s
QPI lanes. It has 5.56-B transistors in Intel's 22-nm trigate HKMG CMOS, achieving a 33% performance boost over previous generations.
The chip complexity chart in
Figure 16 shows the trend in transistor integration on a single chip over
the past two decades. While the 1
billion transistor-integration threshold was achieved some years ago,
we now commonly see processors
incorporating more than 5-B transistors on a die.

0.40
0.20

0.010

45 40 32 28 22 20
Technology Node (nm)

0.00

Figure 17: Bit cell and VDD scaling trend for SRAM.

Some outstanding state-of-the-art
paper topics from ISSCC 2015 include
2
■ two 14-nm SRAM bit cells; 0.050 µm
2
(HDC) and 0.058 µm (LVC) capable of
achieving 1.5 GHz operation at 0.6V
■ a 14-nm FinFET SOI eDRAM with a
cell size of 0.01747 µm2 and 1-ns
access time
■ 128-Gb, 3 b/cell 32 stacked WL
layer 3-D NAND flash running at
1Gb/s I/O rate
■ low-power 64-Gb 2b/cell NAND flash
manufactured in 15-nm technology
■ a 1.1-V, 10-Gb/s/pin transceiver
for DRAM interface suitable for
use beyond LPDDR4

■

a high-speed 1-Mb STT-MRAM using 2T2MTJ cells achieves 3.3-ns
access time and a sub-20-nm technology node STT-MRAM uses a
high-density 1T1MTJ memory cell
a 28-nm embedded SG-MONOS
FLASH developed for automotive
applications.

SRAM
Consumer and computing products
in 2015, from smart watches to the
cloud, depend on low-power and highperformance embedded SRAM. Challenges for SRAM include VMIN, leakage,
and dynamic power reduction. Last

IEEE SOLID-STATE CIRCUITS MAGAZINE

W I N T E R 2 0 15

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2015