IEEE Solid-State Circuits Magazine - Winter 2015 - 23

1,000,000

100,000

Storage Capacity (Mb)

extend the viability of the high-density 6-T SRAM bit cell beyond 14 nm. It
is important for SRAM to reduce both
leakage and dynamic power, keeping
products within the same power envelope at the next technology node. Last
year, the first FinFET-based eDRAM
at 22 nm was introduced. This year,
a 14-nm FinFET-based eDRAM is discussed. eDRAM continues to show
itself as a desirable way to provide
memory scaling in high-performance
CPU designs. Figure 17 shows the
trends in bit-cell and VDD scaling for
SRAMs from major semiconductor
manufacturers.

10,000

100

32 Gb
8 Gb

PRAM

PRAM
128 mb

FeRAM

64 Mb
10

1
2000

MRAM

2002

2004

2006

2008
Year

2010

2012

2014

2016

Figure 20: Trends in NVM technology capacities.

1,000

100

MB/mm2

Nonvolatile Memory
Trends in the density and speed of
nonvolatile random access memory
(NVRAM) continue to show density
and speed advancements. Figure 19
compares NAND/NOR flash write/
read bandwidths to emerging NVRAM
including magnetic random access
memory (MRAM), ferroelectric RAM
(FeRAM), resistive RAM (ReRAM or
RRAM), embedded MRAM (eMRAM),
and phase-change RAM (PRAM). The
performance of embedded NOR Flash
(eNOR) is also seen in this figure. Figure 20 details the changes in density
for these various technologies. It's
interesting to note that NAND flash
density has leveled off the last few
years despite the higher density stored
per cell, as shown in Figure 21, including
triple-level cell (TLC, eight levels or
3 b) and higher density per mm2 of
chip area. Of further interest is the
trajectory of the resistive memory
technologies including RRAM and
PRAM seen in Figure 21. If this trend
continues, it appears that resistive
NVM technologies will replace flash
memory in the near future.

Cond. 1 mb
ISSC, VLSI Circuits, ASSCC,
IEDM, VLSI Tech.

1,000

High-Bandwidth DRAM
To reduce the bandwidth gap between
main memory and processor performance, DRAM data rates continue to
increase at the memory interface with
schemes such as DDR(x), LPDDR(x), and
GDDR(x), as shown in Figure 18. Notable
in Figure 18 is the introduction of the
hybrid memory cube.

128 Gb

NAND Flash

x 1.56/Year

1
1 b/Cell (SLC)
2 b/Cell (MLC)
3 b/Cell (TLC)
4 b/Cell (16LC)

0.1

0.01
1994 1996 1998 2000 2002 2004 2006 2008 2010 2012 2014 2016
Year
Figure 21: Trends in the density of NAND flash memory.

Innovative Topics-Sensors,
MEMS, and Medical Devices
Subcommittee Chair: Makoto Ikeda,
University of Tokyo, Japan
CMOS temperature sensors continue
to improve, with new circuit techniques increasing accuracy and supporting wider applications. Strides
in low-power architectures for such
sensors continue to eclipse previous results with record-setting efficiency that support battery-operated

and mobile applications. Pure digital implementations are often used
in thermal monitoring for large
SoCs, which is an important application where small sensor area is a
key feature.
Current sensors are becoming
more integrated and precise. These
devices detect the magnetic field
around a wire or trace carrying a current, and they are used, for instance,
in electrical motor drives, solar power,
and battery-charger applications.

IEEE SOLID-STATE CIRCUITS MAGAZINE

W I N T E R 2 0 15

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2015