IEEE Solid-State Circuits Magazine - Winter 2016 - 13

that the rejection at relatively large
values of | fin - fLO | is limited to
R sw / (R S + R sw) because the ideal commutated network itself exhibits a negligibly small impedance. To minimize
R sw, the width of the switches must be
increased, demanding a higher power
consumption in the LO path.
The magnitude of Z AB at fin = fLO
in Figure 6(b) is about 7 dB lower
than the source resistance. Why does
this happen? Let us plot the steadystate output voltage as shown in
Figure 10, noting that the voltage
on, say, C 1 begins and ends at the
same value, V1, in every other half
of the LO cycle. If I in = I 0 sin ~ LO t
and the discharge of C 1 through R 1
is expressed as V1 exp [- t/ (R 1 C 1)],
one can prove that V1 . 2R 1 I 0 /r
provided that R 1 C 1 & TLO . That is,
VAB (t) can be approximated by a
square wave having a peak-to-peak
amplitude of 4R 1 I 0 /r. It is remarkable that the circuit generates a
square-wave voltage in response to a
sinusoidal current-as if it contained
harmonically scaled resonators at
fLO, 3fLO, etc. Since the first harmonic of VAB has a peak amplitude of
(2R 1 I 0 /r) (4/r) = (8/r 2) R 1 I 0, we conclude that the impedance at fin = fLO
is equal to (8/r 2) R 1 . 0.81R 1, about
1.8 dB lower than R 1 .
The other 5-dB reduction in the
peak impedance in Figure 6(b) arises
from the overlap between the LO
phases. Creating a temporary resistive path between the top terminals of
C 1 and C 2, the overlap may simply
occur because LO and LO have finite
rise and fall times, keeping the two
switches on simultaneously twice
per period [Figure 11(a)]. The resulting differential discharge of C 1 and
C 2 can be attributed to an equivalent
resistance [Figure 11(b)] given by
T
R eq = 2R sw 1 LO ,
2 DT

(1)

where 2R sw is prorated according to
the fraction of the period during which
the switches are on, and the factor of

CB
L1

L2
Vout

+
Vin

-

CESD

RT

Zin

Figure 12: A T-coil network at input.

1/2 accounts for two such events per
LO cycle. As illustrated in Figure 11(c),
this effect translates to a resistance of
R eq /2 in parallel with each capacitor
and hence parallel with Z AB .

VDD
RD
L2
CB

Questions for the Reader
1) The commutated capacitors of
Figure 6(a) are placed at the antenna port of a GSM receiver so

Vin

M1

L1

C1 Ls

Vout

CL

Series
Peaking

Figure 13: A T-coil network at output.

Translational
circuits can shift
an impedance to
a well-defined
center frequency.

as to attenuate by 20 dB a 0-dBm
blocker at 20-MHz offset. What
issues does such a circuit face?
2) Does V0 in Figure 10 change if
the circuit contains four capacitive branches that are driven by
25% duty-cycle LO phases?

Answers to Last Issue's Questions
1) Use a power dissipation argument
to determine the transfer function
of the circuit shown in Figure 12.
We know that Z in = R T at all frequencies. That is, the power delivered by Vin to the circuit is equal
to V 2in, rms /R T . For a lossless T-coil
network, all of this power is delivered to R T , generating an output
equal to the input. The transfer
function is thus equal to one.

2) In Figure 13(a), how should L S be
chosen if the damping factor of
the series peaking network must
remain around 2 /2?
Since the resistance seen by
L S on the right is equal to R D, we
reduce the circuit to the series
combination of C 1, L S , and R D .
For this network to have a damping factor equal to 2 /2, we
have g = (R D /2) C 1 /L S = 2 /2
and hence L S = R 2D C 1 /2.

References

[1] H. Busignies and M. Dishal, "Some relations between speed of indication, bandwidth, and signal-to-random-noise ratio
in radio navigation and direction finding," Proc. IRE, pp. 478-483, May 1948.
[2] W. R. LePage et al., "Analysis of a comb filter using synchronously commutated capacitors," ASEE Proc., pp. 63-68, May 1953.
[3] B. D. Smith, "Analysis of commutated networks," IRE Trans. Prof. Group Aeronaut.,
pp. 21-26, Dec. 1953.
[4] L. E. Franks and I. W. Sandberg, "An alternative approach to the realization of network
transfer functions: The N-path filter," Bell
Syst. Tech. J., pp. 1321-1350, Sept. 1960.

IEEE SOLID-STATE CIRCUITS MAGAZINE

W I N T E R 2 0 16

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