IEEE Solid-State Circuits Magazine - Winter 2016 - 37

A major goal of our investigation was to predict the mismatch in
drain current over a wide range of
operating conditions using a minimum set of measured data. This can
be accomplished by characterizing
the mismatch in various parameters
of a circuit model. As an elaborate
circuit model may greatly exceed
the accuracy of measurable data or
even hamper the extraction of statistically significant model parameters, we chose the simple square-law
model. The current-voltage relationship in the triode region is given by
I = K c VGS - VT -

VDS m
VDS .
2

(1)

The statistically significant parameters are the threshold voltage VT
and conductance constant K, which

are the intercept and slope, respectively, of (1) for very small values of
VDS . Variations in the various charge
quantities and in the gate oxide
capacitance contribute to mismatch
in VT . The sources of mismatch for
the conductance constant are channel mobility, gate oxide capacitance,
and dimensional variations. The correlation between the mismatches in
VT and K was theoretically derived
and experimentally verified and was
found to be close to zero. Therefore,
the mismatch in drain current in saturation region is simply given by
v 2I
=
I2

2
v VT
v 2K
.
2 +4
(VGS - VT ) 2
K

(2)

Mismatches in VT and K were
separately measured and used in (2)

to estimate the mismatch in current
at two different values of VGS . The
mismatch in current was also directly
measured at these gate voltages and
was found to agree well with the calculated values, thus validating the
mismatch models as well as the characterization methodology.
These mismatch models are
valid across a wide range of dimensions. As the threshold voltage of
small geometry devices is a function of channel length and width,
we examined the threshold voltage
mismatch caused by dimensional
variations. We found that the mismatch component of the threshold
voltage brought about by the dimensional variations is only 10% of the
total threshold voltage mismatch.
Thus, these models are valid for

Working With prof. copeland
It has been over three decades since I first contacted Prof. Copeland,
yet I vividly remember everything that led to my arrival at Carleton
University. Upon receiving my master's degree in electrical communication engineering from the Indian Institute of Science (IISc), Bangalore, India, I took up an industry job. Later I decided to pursue doctoral
studies under an eminent person. I came across many papers from
Prof. Copeland in IEEE journals. With the expectation of having a wellknown expert in the field as both my mentor and guide, I wrote to him
expressing my desire to study and work with him.
Very promptly, I received a reply encouraging me to apply to Carleton University. He also mentioned that there was very little time left
to enroll for the fall 1981 term, particularly because Canada Post was
on strike. Incidentally, mail to and from Carleton was going through
Ogdensburg, New York to circumvent the Canadian postal system.
Prof. Copeland's genuine concern for me became evident even before
I formally became his student, which prompted me not to apply to any
other university. Simultaneously, I applied for the Canadian Commonwealth Scholarship and was lucky to be one of the few applicants to
receive it. Finally, a week after the fall 1981 term had begun, I arrived
at Carleton University ready and anxious to begin my long and fruitful
association with Prof. Copeland.
Prof. Copeland was kind enough to introduce me to Bob Hadaway
of Northern Telecom (see Figure S5 for a recent photo of the three of
us), who would lend me support in the area of IC design, which proved
crucial to my Ph.D. thesis. Bob's goal was to gather data regarding mismatch in MOS current sources rather than doing circuit design, which
was dear to me. However, he would let me test out circuit ideas as long
as our work remained synergistic. The test structures were in a new

3-μm process being developed at Northern Telecom (later Nortel), and
it took about nine months to fabricate our first silicon. Prof. Copeland
never put any demands on me about publications, reports, etc. In fact,
he assured me that I would know when my research was complete.
Indeed, when I thought my work was worthy of a doctoral dissertation,
there was no reservation of any kind. Thus, I received my degree after
four years. I enjoyed the utmost freedom one could hope for under Prof.
Copeland's and Bob's supervision. I will cherish the memory of those
days for as long as I live.

Figure s5: The author (left) with mentors Robert Hadaway
(center) and Miles Copeland at a celebration in honor of Prof.
Copeland at Carleton University on 13 April 2013.

IEEE SOLID-STATE CIRCUITS MAGAZINE

W I N T E R 2 0 16

Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016