IEEE Solid-State Circuits Magazine - Winter 2016 - 55

What is the voltage across the
diode and capacitor of the SP cell?
As can be seen in Figure 4(a), the
capacitor voltage in parallel state is
equal to VIN and that in serial state
is lower than VIN by Q/C. Therefore, the capacitor could be made of
a low-voltage device, which enables
the reduction of the capacitor area
with higher capacitance density.
On the other hand, the switches
used closely to the output terminal
see N times higher than VIN for
both states, resulting in a requirement for high-voltage switching
devices. To integrate voltage multipliers in ICs, you have to take
the impact of parasitic capacitance
into consideration.
We know the SP works by changing the state alternately. When all
the capacitors are connected in
parallel with the power supply,
there is no impact of the parasitic
capacitance on the stored amount of
charge in the capacitors. As shown
in Figure 4(c), when the capacitors
are connected in series, if the parasitic capacitance (C p) is negligibly
small, each capacitor transfers a
same amount of charge Q to the
next capacitor, resulting in outputting Q. However, if the parasitic
capacitance is not negligible, the
transferred charge is reduced at
every node. To be worse, the charge
loss at an upper node is larger than
that at a lower node. The k th node
has a voltage amplitude of k Vin
from the parallel to in-series period.
Thus, the k th capacitor reduces the
charge proportional to k Vin . The
sum of charge loss from the bottom
to the top would be proportional to
N 2 [14], [15]. This means that the
charge loss increases as the voltage
gain increases. As a result, serial
connection can lose voltage gain
significantly.

Falkner Parallel (1973) Figure 5
Falkner showed another voltage
multiplier topology with lower
output resistance using parallel
configuration with a three-phase
clock as shown in Figure 5 [6]. The

VIN
V IN

N × VIN

In Parallel

VOUT
GND

In Series

VIN

N × VIN
VOUT
GND

(N + 1) VIN

(a)

In Parallel

In Series

VIN

N-Caps

Q

Q

VOUT

VCAP
VIN

0V
VCAP = VIN - Q/C

(b)

VOUT = VIN + N VCAP
= (N + 1)VIN - N Q/C

w/Cp

No Cp

Q - (q1 + ... + qN) ∝ N2

Q

Charge Loss Σ qk

qN
Q

qk ∝ k VIN

Q - (q1 + ... + qN-1)

q2

Q

VIN

0V
Q - q1

q1

Q

Q
VIN

VIN
(c)

Figure 4: (a) a serial/parallel voltage multiplier [5]. (b) a serial/parallel [5]. (c) a serial/
parallel [5].

Capacitors in Parallel Rather Than in Series with Modern Transistors
VOUT

0V

CT
Φ1

Φ2

Φ3

Φ1

Φ2

Φ3

CB
Figure 5: parallel configuration for lower output impedance [6].

IEEE SOLID-STATE CIRCUITS MAGAZINE

W I N T E R 2 0 16

55



Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016

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