IEEE Solid-State Circuits Magazine - Winter 2016 - 56
100 µm
VOUT
VIN
Φ1
Φ2
(b)
Q-q
q
Q-q
q
q
q
Q
Q
0V
VIN
Multiplier Chain
Oscillator
Clock Drivers
Output Limiter
(a)
(k - 1)th
VIN
k th
(k + 1)th
0V
VIN
0V
(k - 1)th
k th
(k + 1)th
(c)
Figure 6: The first si verified on-chip voltage multiplier [7].
1
2
1
2
2
1
2
1
1
2
1
1
2
Load
VIN
VOUT
GND
(a)
N
Voltage Gain:
VOUT_MAX/VIN
1
2
2
3
3
5
4
8
5
Dickson First Si Verified On-Chip
Voltage Multiplier (1976) Figure 6
13
(b)
1VIN
3VIN
2VIN
3VIN
3VIN
8VIN
5VIN
VOUT
Load
1VIN
VIN
Phase 1
GND
1VIN
2VIN
2VIN
5VIN
3VIN
5VIN
5VIN
Phase 2
GND
(c)
Figure 7: an sc voltage multiplier with smaller number caps [8].
56
W I N T E R 2 0 16
IEEE SOLID-STATE CIRCUITS MAGAZINE
Load
2VIN
VIN
key point is that each capacitor is
connected with a next neighbor in
parallel in each phase. The number of switches or diodes are that
of capacitors plus one, which is
the same condition as the CW. The
bottom plate capacitance is moved
from a high-voltage path to a lowvoltage path, therefore it should
have less dependence of parasitic
capacitance on the voltage gain.
In 1976, Dickson theoretically and
experimentally, for the first time,
studied an on-chip high-voltage
generator including a voltage multiplier, oscillator, clock drivers, and
a limiter as shown in Figure 6(a)
[7]. The diode is made of a MOSFET
whose gate and drain terminals are
connected, as shown in Figure 6(b).
Dickson used a two-phase clock,
which allowed the clock frequency
as fast as possible. Using a sevenstage voltage multiplier, he successfully generated 40 V from the power
supply voltage of 15 V.
The effective output impedance
R PMP and the maximum attainable
voltage VMAX are calculated as follows. When the input terminal is
connected with VIN, VMAX is as high
as (N + 1) VIN when the number of
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016
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