IEEE Solid-State Circuits Magazine - Winter 2016 - 57

I OUT = fC ((N + 1) VIN - VOUT) /N.

In the 1990s, concerns about the SC voltage
multipliers were the reduction in the number of
capacitors and switching devices for discrete highpower applications.

(2)

Because the amount of output
charges per cycle (Q) is I OUT /f, (2) is
identical to (1). Thus, an ideal parallel voltage multiplier has the exact
same characteristic as an ideal SP
multiplier.
What about the impact of parasitic capacitance on the Falkner/
Dickson parallel voltage multiplier? The charge supplied from
the power supply is Q independent of the capacitor location.
Assuming each capacitor loses q,
every capacitor can transfer Q - q
independently of the capacitor
location unlike the SP as shown in
Figure 6(c) [14], [15]. Thus, parallel connection allows the parallel
multiplier to have many input terminals, resulting in low loss in the
voltage gain. A drawback is that
capacitor needs to be composed on
high voltage devices.

Another multiplier having a smaller
number of stages is Cernea's 2N
multiplier, as shown in Figure 8(a)
[9]. When the number of stages connected between the input and the
output is N, the required number
of capacitors are 2N because two
arrays are required to complete the
multiplier unlike the other types

gnd
2

2

VIN

VIN

2

2

1

1

1

1

2

2

2

2

1

1

1

1

1

2

2

2

2

2

1

Ueno Fibonacci (1991) Figure 7
In the 1990s, concerns about the SC
voltage multipliers were the reduction in the number of capacitors
and switching devices for discrete
high-power applications. Ueno et
al. proposed, in 1991, a multiplier,
as shown in Figure 7(a), whose maximum attainable voltage is given
by the Fibonacci number when
I OUT = 0, as shown in Figure 7(b)
[8]. Each box of Figure 7(a) indicates a switch, and 1 and 2 means
the switch turns on in phase 1 or
2, respectively. In phase 1, an even
number of stages are connected
in series with the output terminal and odd number of stages are
connected in parallel to the serial
one as shown in Figure 7(c). In
phase 2, the situations are complementary. Thus, half of the stages
are in series, and the other half are

Cernea 2 N (1995) Figure 8

in parallel. Capacitors and diodes
need to be high-voltage devices. As
the number of stages increases, the
voltage gain increases more rapidly
than the number of stages. Each
stage has one capacitor and three
switches. Theoretically, it is proven
that this topology has the smallest number of stages in two-phase
clock multipliers [25].

1

VOUT

1

1

Load

stages or capacitors is N. It is well
known that the effective resistance
of an SC is 1/ (fC ), where f is the
clock frequency. Thus, a parallel
voltage multiplier with N-stages has
R PMP of N/ (fC). As a result,

gnd
(a)
gnd

Phase 1
2VIN
1VIN

VIN

8VIN
4VIN

4VIN
2VIN

16VIN
8VIN

VOUT

gnd
gnd

VIN

Phase 2

1VIN

2VIN

4VIN

8VIN

2VIN

4VIN

8VIN

16VIN

VOUT

gnd
(b)

Figure 8: an sc voltage multiplier with smaller number stages [9].

IEEE SOLID-STATE CIRCUITS MAGAZINE

W I N T E R 2 0 16

57
Table of Contents for the Digital Edition of IEEE Solid-State Circuits Magazine - Winter 2016
